Patent classifications
G06F3/0602
MANAGING ADDRESS ACCESS INFORMATION
Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.
Data storage performance scaling based on external energy
Systems and methods are disclosed for data storage performance scaling based on external energy. In certain embodiments, a system may comprise a data storage device having an interface to communicate with an external device, a nonvolatile memory, and a circuit. The circuit may be configured to receive an indication via the interface of power resources available to the data storage device from the external device in case of a power loss event, adjust a performance metric of the data storage device to apply when accessing the nonvolatile memory during normal power availability based on the indication, and perform operations during normal power availability based on the performance metric.
Consolidated Write System and Method
A method, computer program product, and computing system for receiving a plurality of discrete write requests on a first computing device until the end of a consolidation window; combining the plurality of discrete write requests received into a consolidated write request; and transmitting the consolidated write request to a second computing device.
Method and apparatus for bad block management in flash memory
A method of managing blocks in a flash memory includes: detecting states of blocks of a reserved area in the flash memory and building a bad block management table accordingly; recording mappings between bad blocks of an user area in the flash memory and good blocks of the reserved area into the bad block management table; when the bad block management table indicates there is no good block remaining in the reserved area that can be mapped to, selecting one of bad blocks of the reserved area or the user area and obtaining a recollected block after erasing the selected bad block; recording a mapping between the recollected block and a bad block in the user area into the bad block management table; and based on the bad block management table, programming data into the recollected block.
Programmable logic controller, external apparatus, method, and recording medium
A programmable logic controller performs execution of a program in each set period and repeats the execution of the program. The first device storage stores a device value that is an input value and an output value of the program. The second device storage stores the device value stored in the first device storage in a previous period. In a case in which a reading target preset for a device designated by a monitor request received from an engineering tool is the first device storage, the command processor reads the device value stored in the first device storage after execution of the program in a current period is completed, and in a case in which the reading target is the second device storage, the command processor immediately reads the device value stored in the second device storage. The command transmission/reception element transmits the device value to the engineering tool.
DATA STORAGE DEVICE IDENTIFYING TENANTS AND OPERATING METHOD THEREOF
A data storage device includes a volatile memory device including a first table area storing a first table having a plurality of first unit information, and a nonvolatile memory device including a subtree area and a second table area. The second table area stores sorted string tables (SSTables) of level 0 each including a respective plurality of first unit information. Each first unit information includes a key corresponding to a key-value (KV) command and a namespace identifying a tenant providing that KV command. The second table area and the subtree area form a data structure which can be queried with a key included in a KV command. The subtree area includes a plurality of subtrees respectively corresponding to a plurality of namespaces, each subtree storing an SSTable of level 1 having a plurality of second unit information each having a key related to the corresponding namespace of that subtree.
ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.
MEMORY SYSTEM FOR MANAGING DATA CORRESPONDING TO A PLURALITY OF ZONES AND OPERATING METHOD THEREOF
The embodiments of the present disclosure relate to a memory system for managing data corresponding to a plurality of zones and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to write data corresponding to a plurality of zones to a first area including two or more of the plurality of memory blocks, flush the data corresponding to a first zone among the plurality of zones to a second area including two or more of the plurality of memory blocks on determination that a flush condition set for the first zone is satisfied.
Alleviating Interconnect Traffic in a Disaggregated Memory System
One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.
Consolidated write system and method
A method, computer program product, and computing system for receiving a plurality of discrete write requests on a first computing device until the end of a consolidation window; combining the plurality of discrete write requests received into a consolidated write request; and transmitting the consolidated write request to a second computing device.