Various embodiments provide an electronic device and a method, the electronic device comprising: a memory; a first processor; a second processor which has attributes different from those of the first processor; and a control unit, wherein the control unit is configured to identify a task loaded into the memory, select which of the first processor and the second processor is to execute the task, on the basis of attribute information corresponding to a user interaction associated with the task, and allocate the task to the selected processor. Other embodiments are also possible.

A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.

A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.

A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.

A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.

A method, computer program product, and system for managing parallel microservices are provided. The method may include identifying information pertaining to each of a plurality of target microservices to be invoked by an issuer microservice, a predefined condition associated with the plurality of target microservices, and an action to be executed by the issuer microservice in response to the predefined condition being satisfied. The method may also include sending a first request to available target microservices of the plurality of target microservices based on the information pertaining to the respective available target microservices. The method may also include, in response to receiving a response to the first request from an available target microservice of the available target microservices, determining whether the predefined condition is satisfied, and in response to determining that the predefined condition is satisfied, causing the action to be executed by the issuer microservice.

A method, computer program product, and system for managing parallel microservices are provided. The method may include identifying information pertaining to each of a plurality of target microservices to be invoked by an issuer microservice, a predefined condition associated with the plurality of target microservices, and an action to be executed by the issuer microservice in response to the predefined condition being satisfied. The method may also include sending a first request to available target microservices of the plurality of target microservices based on the information pertaining to the respective available target microservices. The method may also include, in response to receiving a response to the first request from an available target microservice of the available target microservices, determining whether the predefined condition is satisfied, and in response to determining that the predefined condition is satisfied, causing the action to be executed by the issuer microservice.

A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.

A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.

Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.