This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

A method for execution by transition storage facility includes determining to initiate capturing snapshot information from a plurality of modules of a dispersed storage network (DSN). Snapshot scheduling information is issued to a plurality of modules of the DSN. The plurality of modules, in response to receiving the snapshot scheduling information, capture the snapshot information. The snapshot information is received from the plurality of modules, and the snapshot information is stored in temporary storage. A storage operations approach is selected for utilizing the temporarily stored snapshot information, and execution of the storage operations approach is initiated.

A safety-relevant computer system, in particular a railway safety system, contains at least two hardware channels. A memory check results of the channels are fed to at least one comparator, which triggers an error response if the memory check results are not equal. In order to be able to use diverse software programs created by compilers, memory check results of the diverse software programs of each channel are fed to the comparator. The memory check results of a first software program of the first and second channels are compared with each other and the memory check results of a second software program of the first and second channels are compared with each other.

An information processing apparatus includes a storage device, an arithmetic processing unit, a first converting device, and a second converting device. The storage device outputs data in accordance with a memory access request. The arithmetic processing unit performs an arithmetic operation on the data. The first converting device converts a memory access request issued by the arithmetic processing unit to a memory access signal and sends to the storage device. The second converting device converts a memory access request issued by the arithmetic processing unit to a memory access signal, acquires the memory access signal sent by the first converting device, and compares the content of a memory access performed by using the converted memory access signal with the content of a memory access performed by using the acquired memory access signal, and determines whether the first converting device has failed.

Systems and methods are provided for flash memory devices to improve the write performance in case of write path errors and to hide the write path error correction latency. Some embodiments can provide instant parity correction to allow user data sharing the same strip with the data block having an error to be programmed into the flash memory before the failed data is corrected. Additionally, selected stalling can allow some independent data in different flash memory dies or planes to be programmed during the time of write path error correction.

A data processing network for performing successive data processing steps in a redundant and validated manner. Each step is used to generate output data from input data. Output data from a first data processing step are at least partially simultaneously input data of a further data processing step. At least one first data processing module is provided for performing each data processing step. The data processing network also includes a comparator module. The first data processing modules transmit control parameters of the individual data processing steps to the comparator module. The comparator module is provides a synchronized control parameter which contains control information relating to at least one performed data processing step. The data processing network includes a recording module in which a debug mode can be activated with which debug data containing information on each execution of a data processing step with the data processing network are recorded.

A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal.

This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error.

Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.