G06F11/261

CLOUD SIMULATION AND VALIDATION SYSTEM

Cloud simulation or validation system allows for the simulation of a future node that may be deployed on a piece of hardware. The system may attempt to simulate the operating system for node-A on top of the hardware for node-A, including basic network connectivity. When a host is booted up with the simulated configuration, validation scripts may be run to verify that the site is correctly prepped for cloud deployment. With its pre-staged RAM-based OS temporarily loaded into the host's RAM memory, any set of OS-based scripts, tools or binaries, may be executed for simulation and validation based upon the intended role of the host onto which the cloud simulation or validation system configuration is loaded.

SIMULATION SYSTEM FOR ACCIDENT ANALYSIS OF AUTONOMOUS EMERGENCY BRAKING DEVICE AND SIMULATION METHOD THEREOF
20230350779 · 2023-11-02 ·

Provided is a simulation system for accident analysis of an autonomous emergency braking device, the simulation system including a data input unit configured to receive virtual driving data including state data about a virtual driving vehicle, a target, and a driving environment; a radar driving logic unit configured to calculate a relative speed, a relative distance, and an azimuth between the virtual driving vehicle and the target based on the virtual driving data; and an autonomous emergency braking driving logic unit configured to output a warning signal or apply a braking pressure to the virtual driving vehicle according to a sequence of the autonomous emergency braking device, and to calculate collision data including a final stopping distance and a collision speed.

VIRTUALIZATION OF COMPLEX NETWORKED EMBEDDED SYSTEMS

A testing and verification system for an equivalent physical configuration of an in-flight entertainment and communications system with one or more hardware components includes a virtual machine manager. One or more virtual machines each including a hardware abstraction layer is instantiated by the virtual machine manager according to simulated hardware component definitions corresponding to the equivalent physical configuration of the hardware components. The virtual machines are in communication with each other over virtual network connections. A test interface to the one or more virtual machines generate test inputs to target software applications installed on the virtual machines. A display interface is connected to the virtual machines, with results from the execution of the target software applications responsive to the test inputs are output thereto.

Future proofing and prototyping an internet of things network

A system and method for representing events that occur in a real world deployment is described. A real-world workload including multiple events is identified. Multiple characteristics of the real-world workload are converted into multiple endpoint simulator workloads. Multiple gateway hardware characteristics are converted into a modeling elements for simulated Internet of things (IoT) networks. Further, a simulation is performed for each of the endpoint simulator workloads on each of the simulated IoT networks. Also, statistics are collected about the performance of the simulated IoT networks for the endpoint simulator workloads.

Integrated equipment fault and cyber attack detection arrangement

An integrated vehicle health management (IVHM) system to resolve equipment-fault related anomalies detected by cyber intrusion detection system (IDS). A benefit of the present system is that it can result in fewer alerts that need manual analysis. A combination of cyber and monitoring with integrated vehicle health management (IVHM) may be a high value differentiator. As a solution gets more mature through a learning loop, it may be customized for different customers in a cost effective manner, something that might be expensive to develop on their own for most original equipment manufacturers (OEMs). An IVHM symptom pattern recognition matrix may link a pattern of reported symptoms to known equipment failures. This matrix may be initialized from the vehicle design data but its entries may get updated by a learning loop that improves a correlation by incorporating results of investigations.

Cloud simulation and validation system

Cloud simulation or validation system allows for the simulation of a future node that may be deployed on a piece of hardware. The system may attempt to simulate the operating system for node-A on top of the hardware for node-A, including basic network connectivity. When a host is booted up with the simulated configuration, validation scripts may be run to verify that the site is correctly prepped for cloud deployment. With its pre-staged RAM-based OS temporarily loaded into the host's RAM memory, any set of OS-based scripts, tools or binaries, may be executed for simulation and validation based upon the intended role of the host onto which the cloud simulation or validation system configuration is loaded.

Method for testing at least one control device function of at least one control device
11377115 · 2022-07-05 · ·

A simulator and a method for testing a control device function of a control device of a vehicle. The vehicle includes various environmental sensors, such as radar, a camera, and a radio receiver, which serve as inputs to the control device function of the control device. A corresponding simulation utilizing a vehicle model sensor models, and an environmental model is executed in a distributed fashion via a plurality of computing units and a memory of a simulator. The simulation utilizing the vehicle model, the sensor models, and the environmental model provides inputs to the control device function. Moreover, the simulation utilizing these models is started synchronously on the computing units, wherein data exchange occurs amongst the memory and the multiple computing units.

Integrated circuit device with integrated fault monitoring system

An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR IMPAIRMENT TESTING USING AN EMULATED SWITCHING FABRIC ENVIRONMENT
20220253324 · 2022-08-11 ·

One method occurs at an impairment test system. The method includes receiving test configuration information for configuring a testing environment comprising an emulated switching fabric environment implemented using at least one switching application-specific integrated circuit (ASIC), wherein the test configuration information includes testing environment target state information; configuring, using the test configuration information, an impairment test session involving a system under test (SUT) and the emulated switching fabric environment; wherein configuring the impairment test session includes configuring at least one impairment controller for impairing the testing environment during the impairment test session; and initiating the impairment test session, wherein initiating the impairment test session includes generating and sending, using at least one traffic generator, test traffic via the emulated switching fabric environment and effecting at least one impairment of the testing environment during the impairment test session using a feedback control loop and the at least one impairment controller.

Emulation system supporting computation of four-state combinational functions

An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.