A set command is issued to transfer a diagnostic parameter record to a communication component of the computing environment. The diagnostic parameter record specifies a diagnostic action to be taken by the communication component to obtain diagnostic information and specifies a version of the diagnostic information to be obtained. Based, in part, on issuing the set command, the diagnostic information is obtained. The version of the diagnostic information obtained is the version specified, based on the version specified being supported by the communication component.

In some embodiments, a method for cluster resource scheduling, includes determining at least one load score; determining a memory score; determining an IO score; and monitoring a message bus for candidate messages when each of the at least one load score, memory score, and IO score is less than a pre-determined health threshold. In some embodiments, a host computer system for hosting a plurality of virtual machines (VMs), includes: a memory; a network adapter for communicating with the cluster by way of a message bus; a processor in electronic communication with the memory and the network adapter, wherein the processor is programmed to: determine at least one load score; determine a memory score; determine an IO score; and monitor the message bus for candidate messages when each of the at least one load score, memory score, and IO score is less than a pre-determined health threshold.

An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.

Embodiments of a method, an IC device, and a circuit board are disclosed. In an embodiment, the method involves at an IC device of the system, monitoring activity on a bus interface of the IC device, wherein the bus interface is connected to a bus on the system that communicatively couples the IC device to at least one other IC device on the system, applying machine learning to data corresponding to the monitored activity to generate an activity profile, monitoring subsequent activity on the bus interface of the IC device, comparing data corresponding to the to subsequently monitored activity to the machine learning generated activity profile to determine if a system-level Trojan is detected, and generating a notification when it is determined from the comparison that a system-level Trojan has been detected.

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

An FPGA upgrade method is provided, including: delivering, by a host, an upgrade instruction to an FPGA; uninstalling a PCIe driver corresponding to the FPGA to let a status of the PCIe link be changed to link down; continuously monitoring, in a first expiration time, whether the status of the PCIe link is changed to link up; and if yes, reloading the PCIe driver. The method further includes: after the FPGA receives the upgrade instruction, continuously monitoring, in a second expiration time, whether the status of the PCIe link is changed to link down, if yes, loading the configuration data from the FPGA configuration memory for upgrade; and after upgrade is completed, negotiating, by the FPGA, with the host to restore the status of the PCIe link to link up that is used for reloading the PCIe driver upon detection by the host.

Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is riot limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

Buses such as USB4 or Thunderbolt 4 buses may allow for device combinations that actually cannot be accommodated on the bus. A monitoring component, e.g., software and/or hardware component, such as an Operating System (OS) policy manager, may monitor a bus for events identifying changes to devices on the bus. The monitoring component may influence mode changes to hardware/software, such as to the USB configuration, device driver settings, attached device settings, and/or settings for devices attaching to the bus. Influenced changes facilitate accommodating changes to the devices attached to the bus. For example, if a display is attached and it would exceed available bus bandwidth, cause an excess system load, or cause some other problem, rather than fail to enumerate the display, instead hardware and/or software associated with the bus may be influenced to result in a resolution reduction for the display to accommodate it attaching to the bus.

A method, system, and apparatus for fault detection in a microprocessor-based system uses a serial data communication protocol for communications between a peripheral device and a controller. Peripheral device interface circuitry is adapted to intermittently receive input serial data frames from the controller using the serial communication protocol and to intermittently send output serial data frames to the controller using the serial communication protocol. Each output serial data frame includes one or more status bits representing communication status data and one or more data bits representing peripheral device data. The status bits and the data bits are serially followed by at least one fault bit that indicates whether a fault is detected during sending of the output serial data frame.