Systems and methods for load detection on serial communication data lines are provided herein. In certain configurations, a serial communication system includes a data line having a load capacitance and a master device configured to generate a command signal for a slave device to measure the load capacitance on the data line. The system further includes a slave device including a load detector including a controller configured to receive the command signal from the master device, provide a first fixed current to the data line, determine an amount of time elapsed while the data line is driven to a first threshold value, and determine the load capacitance of the data line based on the amount of time elapsed.

A building management system includes a communications bus, and devices coupled to the communications bus. The devices are coupled to the communications bus and configured to communicate on the communications bus using a master-slave token passing protocol. A first one of the devices has an active node table stored therein. The active node table includes multiple nodes. Each node represents one of the devices participating in a token passing ring used to exchange information among the devices via the communications bus using the master-slave token passing protocol. The first device is configured to monitor the active node table for new nodes and to identify a new device communicating on the communications bus in response to a determination that the active node table includes a new node.

A building management system includes a communications bus, and devices coupled to the communications bus. The devices are coupled to the communications bus and configured to communicate on the communications bus using a master-slave token passing protocol. A first one of the devices has an active node table stored therein. The active node table includes multiple nodes. Each node represents one of the devices participating in a token passing ring used to exchange information among the devices via the communications bus using the master-slave token passing protocol. The first device is configured to monitor the active node table for new nodes and to identify a new device communicating on the communications bus in response to a determination that the active node table includes a new node.

A multi-antenna channel device and a configuration method for the multi-antenna channel device are provided. The device includes: a main control chip and radio frequency chips, wherein the main control chip is connected to chip selection signal interfaces of the radio frequency chips via a shared chip selection signal line and is configured to send a chip selection signal to a target radio frequency chip; the main control chip is connected to clock signal interfaces of the radio frequency chips via a shared clock signal line and is configured to send a clock signal to the target radio frequency chip; and the main control chip is connected to data interfaces of the radio frequency chips via a shared data line and is configured to send target serial data to the target radio frequency chip or receive target serial data from the target radio frequency chip.

A multi-antenna channel device and a configuration method for the multi-antenna channel device are provided. The device includes: a main control chip and radio frequency chips, wherein the main control chip is connected to chip selection signal interfaces of the radio frequency chips via a shared chip selection signal line and is configured to send a chip selection signal to a target radio frequency chip; the main control chip is connected to clock signal interfaces of the radio frequency chips via a shared clock signal line and is configured to send a clock signal to the target radio frequency chip; and the main control chip is connected to data interfaces of the radio frequency chips via a shared data line and is configured to send target serial data to the target radio frequency chip or receive target serial data from the target radio frequency chip.

In aspects, a Local Interconnect Network (LIN) communication circuit including a first LIN master associated with a first LIN bus and a second LIN master associated with a second LIN bus is disclosed. A data link is connected between the first and second LIN masters. A first mirroring client is established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and for transmitting the message bits bitwise over the data link. A second mirroring client is established at the second LIN master for receiving the message bits and transmitting them over the second LIN bus. The first and second LIN masters include synchronised schedule tables such that the message bits on the second LIN bus are transmitted in a corresponding slot to the first.

In aspects, a Local Interconnect Network (LIN) communication circuit including a first LIN master associated with a first LIN bus and a second LIN master associated with a second LIN bus is disclosed. A data link is connected between the first and second LIN masters. A first mirroring client is established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and for transmitting the message bits bitwise over the data link. A second mirroring client is established at the second LIN master for receiving the message bits and transmitting them over the second LIN bus. The first and second LIN masters include synchronised schedule tables such that the message bits on the second LIN bus are transmitted in a corresponding slot to the first.

A method for data transmission control of inter field programmable gate array (FPGA) and an associated apparatus are provided. The method includes: utilizing a first register device to latch a set of data from a first FPGA according to a first clock, wherein the set of data is arranged and divided into multiple sets of partial data according to attributes of payloads and pointers; utilizing a time-division multiplexing (TDM) interface to transmit the multiple sets of partial data from the first register device to a second register device according to a TDM clock at multiple time points, respectively; and utilizing the second register device to sequentially receive the multiple sets of partial data, in order to output the set of data to a second FPGA, wherein the second FPGA operates according to a second clock different from the first clock.

A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.