The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.

Communication is performed more reliably. A CCI (I3C DDR) processing section determines status of an index when requested to be accessed by an I3C master for a read operation. An error handling section then controls an I3C slave 13 to detect occurrence of an error based on the status of the index and to neglect all communication until DDR mode is stopped or restarted by the I3C master, the I3C slave 13 being further controlled to send a NACK response when performing acknowledge processing on a signal sent from the I3C master. This technology can be applied to the I3C bus, for example.

Communication is performed more reliably. A CCI (I3C DDR) processing section determines status of an index when requested to be accessed by an I3C master for a read operation. An error handling section then controls an I3C slave 13 to detect occurrence of an error based on the status of the index and to neglect all communication until DDR mode is stopped or restarted by the I3C master, the I3C slave 13 being further controlled to send a NACK response when performing acknowledge processing on a signal sent from the I3C master. This technology can be applied to the I3C bus, for example.

A motor control device drives a motor based on a vehicle signal including drive assist information and performs vehicle control. The motor control device includes: a first controller and a second controller that perform a calculation operation concerning drive control over the motor. A first microcomputer corresponds to a calculation portion of the first controller. A second microcomputer corresponds to a calculation portion of the second controller. The first microcomputer and the second microcomputer mutually transmit and receive operation results by inter-microcomputer communication, or the first microcomputer unilaterally transmits an operation result from the first microcomputer by the inter-microcomputer communication. The first microcomputer and the second microcomputer synchronize timings to start and end control by performing at least one of three types of arbitration processes including: an AND-start arbitration process; an OR-start arbitration process; and a forced arbitration process.

A motor control device drives a motor based on a vehicle signal including drive assist information and performs vehicle control. The motor control device includes: a first controller and a second controller that perform a calculation operation concerning drive control over the motor. A first microcomputer corresponds to a calculation portion of the first controller. A second microcomputer corresponds to a calculation portion of the second controller. The first microcomputer and the second microcomputer mutually transmit and receive operation results by inter-microcomputer communication, or the first microcomputer unilaterally transmits an operation result from the first microcomputer by the inter-microcomputer communication. The first microcomputer and the second microcomputer synchronize timings to start and end control by performing at least one of three types of arbitration processes including: an AND-start arbitration process; an OR-start arbitration process; and a forced arbitration process.

Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

A control method and device for bidirectional communication are provided. A handshake between the master and slave communication units is realized by sending the training sequence. The master communication unit is controlled to obtain control information from the ECU. The control information is packaged into the custom package, and the custom package is encoded. The master communication unit is controlled to send the custom package to the slave communication unit. The slave communication unit decodes, verifies and corrects the custom package. The slave communication unit feeds back the correct message to the master communication unit if the custom package is verified to be correct, else feeds back the error message to the master communication unit. The master communication unit resends the custom package to the slave communication unit if it receives the error information or does not receive any feedback information within the preset time period.

A control method and device for bidirectional communication are provided. A handshake between the master and slave communication units is realized by sending the training sequence. The master communication unit is controlled to obtain control information from the ECU. The control information is packaged into the custom package, and the custom package is encoded. The master communication unit is controlled to send the custom package to the slave communication unit. The slave communication unit decodes, verifies and corrects the custom package. The slave communication unit feeds back the correct message to the master communication unit if the custom package is verified to be correct, else feeds back the error message to the master communication unit. The master communication unit resends the custom package to the slave communication unit if it receives the error information or does not receive any feedback information within the preset time period.

A system-on-chip (SoC) for operating a plurality of different central processing units and a method for operating the same are provided. The SoC includes a plurality of central processing units (CPUs) that execute respective software programs independently of each other, a bus interconnector for connecting the plurality of CPUs, and at least one access control device that is connected to the bus interconnector and controls each access to a physical resource shared by the plurality of CPUs via the bus interconnector, for each CPU.

Methods, systems, and devices for providing computer implemented services using managed systems are disclosed. To provide the computer implemented services, the managed systems may need to operate in a predetermined manner conducive to, for example, execution of applications that provide the computer implemented services. Similarly, the managed system may need access to certain hardware resources (e.g., and also software resources such as drivers, firmware, etc.) to provide the desired computer implemented services. To improve the likelihood of the computer implemented services being provided, the managed devices may be managed using a subscription based model. The subscription model may utilize a highly accessible service to obtain information regarding desired capabilities (e.g., a subscription) of a managed system, and use the acquired information to automatically configure and manage the features and capabilities of the managed systems.