A main board slot power control circuit will select a lowest priority interface card from a plurality of interface cards to reduce operation frequency, when the system power consumption is found to be too large. The main board slot power control circuit includes a power supply module, a control module, and a plurality of slots. The plurality of interface cards is plugged into the plurality of slots. The control module applies different priorities to the plurality of interface cards. The power supply module detects and determines when the system power consumption is greater than a predetermined value, and the power supply module outputs a control signal to the control module accordingly. The control module selects the lowest priority interface card to reduce operation frequency according to the control signal, and then the next lowest and so on until power consumption is found to be sufficiently reduced.

A main board slot power control circuit will select a lowest priority interface card from a plurality of interface cards to reduce operation frequency, when the system power consumption is found to be too large. The main board slot power control circuit includes a power supply module, a control module, and a plurality of slots. The plurality of interface cards is plugged into the plurality of slots. The control module applies different priorities to the plurality of interface cards. The power supply module detects and determines when the system power consumption is greater than a predetermined value, and the power supply module outputs a control signal to the control module accordingly. The control module selects the lowest priority interface card to reduce operation frequency according to the control signal, and then the next lowest and so on until power consumption is found to be sufficiently reduced.

Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.

A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.

A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

A participating station for a bus system and a method for data transmission in a bus system are provided. The participating station comprises a transceiver unit for transmitting a message to and/or receiving a message from a further participating station of the bus system, and a switching unit for switching a connection to at least one further participating station of the bus system between an open and a closed state, wherein the switching unit is designed for the selective connection control of the participating station to at least one further participating station of the bus system on the basis of at least a part of the message received from the transceiver unit.

A participating station for a bus system and a method for data transmission in a bus system are provided. The participating station comprises a transceiver unit for transmitting a message to and/or receiving a message from a further participating station of the bus system, and a switching unit for switching a connection to at least one further participating station of the bus system between an open and a closed state, wherein the switching unit is designed for the selective connection control of the participating station to at least one further participating station of the bus system on the basis of at least a part of the message received from the transceiver unit.

Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master deviceof a plurality of master devices coupled to a respective plurality of slave devices via an internal networkmay implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.