Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master deviceof a plurality of master devices coupled to a respective plurality of slave devices via an internal networkmay implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.

An information processing system according to the present invention includes: a plurality of processing units; a plurality of input/output units controlled by any one of the processing units; a plurality of first connection units connecting one of the processing units to a first communication channel; a second connection unit connecting the input/output units to a second communication channel; a first mediating unit mediating the second communication channel and a communication network, and transmits identifiers of the input/output units via the communication network; and a plurality of second mediating units mediating a connection between the communication network and the first communication channel, receiving the identifier, and, when an identifier of its own is included in the received identifiers, establishing a connection between the input/output unit with the own identifier and the processing unit and detaches connections between the input/output unit with different identifier and the processing unit.

An information processing system according to the present invention includes: a plurality of processing units; a plurality of input/output units controlled by any one of the processing units; a plurality of first connection units connecting one of the processing units to a first communication channel; a second connection unit connecting the input/output units to a second communication channel; a first mediating unit mediating the second communication channel and a communication network, and transmits identifiers of the input/output units via the communication network; and a plurality of second mediating units mediating a connection between the communication network and the first communication channel, receiving the identifier, and, when an identifier of its own is included in the received identifiers, establishing a connection between the input/output unit with the own identifier and the processing unit and detaches connections between the input/output unit with different identifier and the processing unit.

A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.

An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.