A method, computer program product, and system for managing parallel microservices are provided. The method may include identifying information pertaining to each of a plurality of target microservices to be invoked by an issuer microservice, a predefined condition associated with the plurality of target microservices, and an action to be executed by the issuer microservice in response to the predefined condition being satisfied. The method may also include sending a first request to available target microservices of the plurality of target microservices based on the information pertaining to the respective available target microservices. The method may also include, in response to receiving a response to the first request from an available target microservice of the available target microservices, determining whether the predefined condition is satisfied, and in response to determining that the predefined condition is satisfied, causing the action to be executed by the issuer microservice.

A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.

A system and a method are disclosed that provides a data replication management technique for a distributed environment that eliminates a need to order members of a replica set. A node of a node cluster in the distributed system may be configured to send in parallel an IO request to each respective member of the replica set. Reponses are received from members of the replica set that indicate a completion status of the IO request at the replica set member sending the IO response. A request is sent to other nodes of the node cluster to remove a replica from the replica set based on an error response received from the replica. The replica that responded with the error response is removed from the replica set based on an agreement of nodes of the node cluster to remove the replica from the replica set.

A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

A parallel process apparatus connecting electronic controllers via buses includes: a process request acceptance section that accepts process requests to the electronic controllers; and a process execution section that, while multiple process requests are simultaneously accepted, arbitrates the multiple process requests being accepted, and parallelizes multiple processes in accordance with the multiple process requests.

A physical translation switch may have two parallel channel interfaces (e.g., BoW interfaces) and two serial channel interfaces (e.g., XSR interfaces). The translation switch may have a parallel switching fabric for directing input traffic from input ports on a first type of channel interface to output ports of a second type of channel interface. Thus, when one wants to connect a chiplet with a BoW interface to a chiplet with an XSR interface, the translation switch is connected between the chiplets to provide the needed compatibility. The translation switch provides the needed compatible channel interfaces for the chiplets.

There is disclosed integrated circuitry having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.

The present invention discloses a dual-mode USB device, which includes a USB2.0 controller, a dual-mode USB2.0 interface module and a USB interface. The dual-mode USB device alternatively works in a USB2.0 standard mode or a USB2.0 extended mode. In the USB2.0 standard mode, DP and DM signals of the USB2.0 interface are connected to a remote USB interface by DC coupling, and is compatible with remote devices using USB2.0 standard signals and protocols; in the USB2.0 extended mode, DP and DM signals of the USB2.0 interface are connected to the remote USB interface by AC coupling, which is compatible with remote devices supporting the USB2.0 extended mode.

A parallel process apparatus connecting electronic controllers via buses includes: a process request acceptance section that accepts process requests to the electronic controllers; and a process execution section that, while multiple process requests are simultaneously accepted, arbitrates the multiple process requests being accepted, and parallelizes multiple processes in accordance with the multiple process requests.

A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.