A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T.sub.1 . . . T.sub.4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T.sub.1 . . . T.sub.4 at least one of the four signals has an edge to enable clock recovery at the second IC.

High Bandwidth IJTAG Through High Speed Parallel Bus A system in a circuit comprises: a first network (710) configurable to transmit data in parallel in the circuit, the first network (710) comprising circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks (720, 725, 727), each of the plurality of second networks (720, 725, 727) configurable to transmit data in serial in one of the circuit blocks in the circuit; a third network (730) configurable to transmit data in serial in the circuit when being coupled to the plurality of second networks (720, 725, 727); and a plurality of network switching interface devices (740, 745, 747), each of the plurality of network switching interface devices (740, 745, 747) configurable to couple either the first network (710) or the third network (730) to one of the plurality of second networks (720, 725, 727) based on a control signal stored in the each of the plurality of interface devices (740, 745, 747).

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

In some examples, a storage medium stores information relating to reset ports associated with respective virtual machines (VMs) of a plurality of VMs. A controller detects, based on the information, an activation of a first reset port associated with a first VM of the plurality of VMs. In response to the detecting, the controller provides an indication of the activation of the first reset port to a hypervisor that is separate from the controller, the indication to cause the hypervisor to reset the first VM.

A data transmission method includes: obtaining a target data packet to be stored, the target data packet including an address of the target data packet; determining, from predetermined N parallel-to-serial units based on the address of the target data packet, a target parallel-to-serial unit corresponding to the target data packet, the N parallel-to-serial units being connected to N storage control units in one-to-one correspondence; and transmitting, by the target parallel-to-serial unit, the target data packet to a target storage control unit, and storing, by the target storage control unit, the target data packet in a corresponding storage unit. The target storage control unit is a storage control unit, connected to the target parallel-to-serial unit, of the N storage control units. The target parallel-to-serial unit is configured to divide the target data packet into a plurality of data sub-packets.

Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces. In some examples, the device interface is compatible with Peripheral Component Interconnect Express (PCIe) and the storage configuration circuitry is accessible as a physical function (PF) or a virtual function (VF).

A communication device is configured to exchange regular data bidirectionally with counterpart communication device via a regular interface; and to exchange additional data bidirectionally with the counterpart device via an additional interface. The device has a regular pinout corresponding to the regular interface that enables communication of regular data with the counterpart device; and an additional pinout with at least one additional pin, corresponding to the additional interface that enables communication of additional data with the counterpart device. The device has default data handling circuitry communicatively coupled to the additional pin, and configured, in a default mode, to transmit and receive additional default data via the additional pin. The first device has additional function data handling circuitry communicatively coupled to the additional pin and configured, in an active mode, to transmit and receive additional function data via the additional interface.

A parallel process apparatus connecting electronic controllers via buses includes: a process request acceptance section that accepts process requests to the electronic controllers; and a process execution section that, while multiple process requests are simultaneously accepted, arbitrates the multiple process requests being accepted, and parallelizes multiple processes in accordance with the multiple process requests.