An apparatus and method for sensing the position of a piston in a valve in a gas compressor or the position of a piston in a free piston engine. The apparatus includes a plurality of valve sensors, a plurality of magnets, and a plurality of valve sense modules coupled to the valve sensors and a controller coupled to the plurality of valve sense modules. The method includes processing information received from the valve sensors to determine the linear position of the valves in the gas compressor or a piston in a free piston engine.

Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.

Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.

A storage server includes a plurality of solid state drives (SSDs), a plurality of input/output (IO) controllers, and a plurality of fabrics. Each fabric is configured to provide a fully connected mesh topology that connects each of the plurality of IO controllers to each of the plurality of SSDs. Each fabric comprises a management controller, a first switch layer comprising a first plurality of switches coupled to the plurality of IO controllers, and a second switch layer comprising a second plurality of switches coupled to a) the first plurality of switches and b) the plurality of SSDs, The first switch layer and the second switch layer together provide the fully connected mesh topology that connects every IO controller of the plurality of IO controllers to every SSD of the plurality of SSDs.

A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.

A method, computer program product, and system for managing parallel microservices are provided. The method may include identifying information pertaining to each of a plurality of target microservices to be invoked by an issuer microservice, a predefined condition associated with the plurality of target microservices, and an action to be executed by the issuer microservice in response to the predefined condition being satisfied. The method may also include sending a first request to available target microservices of the plurality of target microservices based on the information pertaining to the respective available target microservices. The method may also include, in response to receiving a response to the first request from an available target microservice of the available target microservices, determining whether the predefined condition is satisfied, and in response to determining that the predefined condition is satisfied, causing the action to be executed by the issuer microservice.

A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

A method is provided for performing a secure communication between a real-time operating system and a general purpose operating system. The systems are provided in a single computing apparatus and separated by a virtual machine monitor. The systems include a first and second open platform communications interfaces, respectively. The method includes: receiving a request with the virtual machine monitor from a user via the first or second open platform communications interface to access data of the real-time operating system from the general purpose operating system or to access data of the general purpose operating system from the real-time operating system; establishing a secure communication path via a software bus between the first and the second open platform communications interfaces according to the request; and performing a secure communication between the real-time operating system and the general purpose operating system via. the established secure communication path for accessing the data.

There is disclosed integrated circuitry comprising having a bit receiving arrangement adapted for receiving, in parallel, a plurality of data bits, the bit receiving arrangement further being adapted for receiving a data bit inversion bit associated to the plurality of data bits, the data bit inversion bit being for indicating whether the bits of the plurality of data bits are inverted. The integrated circuitry also comprises has a bit inversion arrangement adapted for inverting the bits of the plurality of data bits based on a comparison between the received data bit inversion bit and an inversion estimate bit, the inversion estimate bit being determined based on the plurality of data bits. The disclosure also pertains to related methods and devices.