A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

Disclosed embodiments relate, generally, to interfacing serial communication interfaces of a first device with a parallel communication interface of a second device. A first group of two or more serial communication interfaces and an interfacing logic may be provided. The interfacing logic may form second encoded data blocks by arranging the data elements of the first encoded data blocks such that data elements within a same data element position of respective second encoded data blocks represent a given one of the symbols, and provide the second encoded data blocks to a number of serial communication interfaces coupled to a parallel communication interface of another device. An interfacing logic may additionally or alternatively be configured to receive, from a second group of two or more serial communication interfaces, received encoded data blocks representing received symbols.

In some examples, a storage medium stores information relating to reset ports associated with respective virtual machines (VMs) of a plurality of VMs. A controller detects, based on the information, an activation of a first reset port associated with a first VM of the plurality of VMs. In response to the detecting, the controller provides an indication of the activation of the first reset port to a hypervisor that is separate from the controller, the indication to cause the hypervisor to reset the first VM.

A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

The present invention discloses a dual-mode USB device, which includes a USB2.0 controller, a dual-mode USB2.0 interface module and a USB interface. The dual-mode USB device alternatively works in a USB2.0 standard mode or a USB2.0 extended mode. In the USB2.0 standard mode, DP and DM signals of the USB2.0 interface are connected to a remote USB interface by DC coupling, and is compatible with remote devices using USB2.0 standard signals and protocols; in the USB2.0 extended mode, DP and DM signals of the USB2.0 interface are connected to the remote USB interface by AC coupling, which is compatible with remote devices supporting the USB2.0 extended mode.

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

Systems and methods according to present principles provide a test architecture which is designed to support software and hardware testing in an automated environment. Systems and methods are described which include a functional definition and architecture of the test system including the host environment, host-user interface, test scripts, host-to-target communications, target test module, target test shell, target commands and other supporting aspects.

An information processing system equipped with an information processing device, which includes multiple processors and a common parallel port (port), and a peripheral device, which includes a data classification means and multiple computing means. Each processor appends each processor identifier to a respective series of codes capable of expressing given data, thereby generating a writing unit capable of being written one time in the bus width of the port, and sequentially writes the writing unit to the port without performing exclusive control. A data classification means reads the writing units from the port sequentially and sequentially outputs the series of codes included in the writing unit to a computing means associated with the processor identifiers included in the writing unit. The computing means reconstructs the original data on the basis of the series of codes.

The present invention relates to a communication chipset, a communication device and a protocol offload method for automatic address allocation, and the communication chipset includes: a plurality of registers for storing address setting modes and IP addresses; a controller-interface for setting the address setting mode on the basis of a data received from a controller controlling an offload device through execution of a program; a network-interface for transmitting and receiving a network packet; and an IP address creation control module for automatically setting an IP address of the plurality of registers using the received network packet according to the set address setting mode.

The present application discloses a gateway device for managing multiple electronic tags. The gateway device includes a network modem configured to receive updated data for multiple electronic tags. Additionally, the gateway device includes a communication chip configured to transmit individual updated data for each individual electronic tag one by one to the corresponding individual electronic tag of the multiple electronic tags. Moreover, the gateway device includes a microcontroller coupled with the network modem and the communication chip to control receiving the updated data for the multiple electronic tags from the network modem and transmitting multiple individual updated data respectively to the multiple electronic tags.