A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

A user station for a serial bus system and a method for error signaling for a message received in a serial bus system are provided. The user station includes a communication control unit for creating a message to be transmitted serially to at least one further user station of the bus system, or for reading a message, received serially from at least one further user station, and a transceiver device for transmitting the created message on a bus line or for receiving a message from the bus line, the communication control unit and/or the transceiver device provide an ACK time window for an ACK signal and/or a NACK time window for a NACK signal in the message to be transmitted for a signaling of whether or not at least one further user station has identified an error in the transmitted message.

A system and a method are disclosed that provides a data replication management technique for a distributed environment that eliminates a need to order members of a replica set. A node of a node cluster in the distributed system may be configured to send in parallel an IO request to each respective member of the replica set. Reponses are received from members of the replica set that indicate a completion status of the IO request at the replica set member sending the IO response. A request is sent to other nodes of the node cluster to remove a replica from the replica set based on an error response received from the replica. The replica that responded with the error response is removed from the replica set based on an agreement of nodes of the node cluster to remove the replica from the replica set.

Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces. In some examples, the device interface is compatible with Peripheral Component Interconnect Express (PCIe) and the storage configuration circuitry is accessible as a physical function (PF) or a virtual function (VF).

A solid state drive having a drive aggregator and a plurality of component solid state drives. The drive aggregator is configured to map logical addresses identified in one or more first commands into multiple logical address groups defined respectively in multiple component solid state drives. According to the one or more first commands and the logical address mapping, the drive aggregator generates multiple second commands and transmits the multiple second commands in parallel to the multiple component solid state drives to perform an operation identified by the one or more first commands.

A first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

Methods and systems support bridging between end devices conforming to a legacy bus specification and a host processor using an updated bus specification, for example the latest PCIe specification or Compute Express Link (CXL). A hardware bridge can serve as an intermediary between the legacy I/O devices and the host processor. The hardware bridge has a hardware infrastructure and performs a hardware virtualization of the legacy I/O devices such that their legacy hardware is emulated by a virtual interface. The hardware bridge can surface the virtual interface to the host processor, enabling these I/O devices to appear to the host processor as an end device communicating in accordance with the updated bus specification. The hardware virtualization can involve emulating the I/O devices using scalable I/O Virtualization (SIOV) queue pairs, providing flexible and efficient translation between the legacy and updated specifications.

A relay device includes end points to relay communication among information processing devices having root complexes connected to the end points. The relay device includes a hardware processor and circuitry. The hardware processor requests one of the devices to set an address space used to access a setting area for the one of the devices. The setting areas are areas in which access information for accessing public areas on memory spaces of the devices are set. The circuitry translates an address input from the one of the devices, based on a translation rule in which an address of the requested address space has been correlated with an address of the setting area for the one of the devices. The translation rule is stored in an area in which the devices are prohibited from performing rewriting.

A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.