A system comprises a plurality of nodes connected in a peer-to-peer network via a communication interface. At least one node of the plurality of nodes comprises a transceiver, at least two connectors, at least one termination resistance module coupled to the transceiver, the at least one termination resistance module providing termination resistance within the node, a first detection circuit coupled to a first connector of the at least two connectors, and a second detection circuit coupled to a second connector of the at least two connectors. The first and second detection circuits are configured to detect that the node is coupled to one or more other nodes in the peer-to-peer network, and automatically adjust the termination resistance based on the detecting.

A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

A system includes a downstream facing port (DFP) coupled to a video source, an upstream facing port (UFP) coupled to a video sink, and a cable. The cable includes a first end that is connected to the DFP and a second end that is connected to the UFP. The cable is configured to carry a differential auxiliary transmission signal and detect polarity in the differential auxiliary transmission signal.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Systems and methods are provided for managing a data communication within a multi-level network having a plurality of switches organized as groups, with each group coupled to all other groups via global links, including: at each switch within the network, maintaining a global fault table identifying the links which lead only to faulty global paths, and when the data communication is received at a port of a switch, determine a destination for the data communication and, route the communication across the network using the global fault table to avoid selecting a port within the switch that would result in the communication arriving at a point in the network where its only path forward is across a global link that is faulty; wherein the global fault table is used for both a global minimal routing methodology and a global non-minimal routing methodology.

Disclosed are a method and a Universal Flash Storage (UFS) system for performing save state switching using selective lanes between a first electronic device and a second electronic device. The method includes: determining, by the first electronic device, whether a data request is received from an application layer of the first electronic device; and performing, by the first electronic device, at least one of: setting a first lane from among a plurality of lanes between the first electronic device and the second electronic device to an active state and the other lanes from among the plurality of lanes to a power save state based on determining that the data request is not received from the application layer of the first electronic device; and setting the plurality of lanes between the first electronic device and the second electronic device to the active state based on determining that the data request is received from the application layer of the first electronic device.

There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.