Concepts, systems and methods are described for generating a quantum circuit from a Unitary Coupled Cluster (UCC) ansatz which represents the excitation of a reference state by a parameterised operator including excitation operators. The UCC ansatz includes multi-qubit Pauli operators, referred to as Pauli strings, determined from each excitation operator. The method comprises partitioning the Pauli strings into mutually commuting sets and sequencing the Pauli strings by set. Pauli gadgets are then generated from the Pauli strings by Trotterization, the Pauli gadgets having the same sequencing by set as the Pauli strings. Each set of Pauli gadgets is diagonalised to convert the Pauli gadgets into phase gadgets which are then transformed into one- and two-qubit native gates to generate the quantum circuit.

Concepts, systems and methods are described for generating a quantum circuit from a Unitary Coupled Cluster (UCC) ansatz which represents the excitation of a reference state by a parameterised operator including excitation operators. The UCC ansatz includes multi-qubit Pauli operators, referred to as Pauli strings, determined from each excitation operator. The method comprises partitioning the Pauli strings into mutually commuting sets and sequencing the Pauli strings by set. Pauli gadgets are then generated from the Pauli strings by Trotterization, the Pauli gadgets having the same sequencing by set as the Pauli strings. Each set of Pauli gadgets is diagonalised to convert the Pauli gadgets into phase gadgets which are then transformed into one- and two-qubit native gates to generate the quantum circuit.

Concepts, systems and methods are described for generating a quantum circuit from a Unitary Coupled Cluster (UCC) ansatz which represents the excitation of a reference state by a parameterised operator including excitation operators. The UCC ansatz includes multi-qubit Pauli operators, referred to as Pauli strings, determined from each excitation operator. The method comprises partitioning the Pauli strings into mutually commuting sets and sequencing the Pauli strings by set. Pauli gadgets are then generated from the Pauli strings by Trotterization, the Pauli gadgets having the same sequencing by set as the Pauli strings. Each set of Pauli gadgets is diagonalised to convert the Pauli gadgets into phase gadgets which are then transformed into one- and two-qubit native gates to generate the quantum circuit.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

A programming language and a compiler are disclosed that optimize the use of look-up tables (LUTs) on a synchronous digital circuit (SDC) such as a field programmable gate array (FPGA) that has been programmed. LUTs are optimized by merging multiple computational operations into the same LUT. A compiler parses source code into an intermediate representation (IR). Each node of the IR that represents an operator (e.g. ‘&’, ‘+’) is mapped to a LUT that implements that operator. The compiler iteratively traverses the IR, merging adjacent LUTs into a LUT that performs both operations and performing input removal optimizations. Additional operators may be merged into a merged LUT until all the LUT's inputs are assigned. Pipeline stages are then generated based on merged LUTs, and an SDC is programmed based on the pipeline and the merged LUT.

A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.

A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.