A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing topological scheduling on a machine-learning accelerator having an array of tiles. One of the methods includes performing, at each time step of a plurality of time steps corresponding respectively to columns within each of a plurality of wide columns of the tile array, operations comprising: performing respective multiplications using tiles in a respective tile column for the time step, computing a respective output result for each respective tile column for the time step including computing a sum of results of the multiplications for the tile column, and storing the respective output result for the tile column in a particular output RAM having a location within the same tile column and on a row from which the output result will be read by a subsequent layer of the model.

An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells and a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank. The memory also comprises a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, and wherein a write verification operation associated with a data word of the second plurality of data words is performed a predetermined period of time after the data word is written into the memory.

An instruction set architecture of a data processing system includes one or more persistent atomic instructions that provide failure-safe atomicity. When issued, a sequence of operations associated with the persistent atomic instruction are performed and first data, associated with a first address in a persistent memory of the data processing system, is written to a point of persistence in the data processing system. Access to data associated with the first address is controlled such that the first data is not available to other execution threads of the data processing system until completion of writing the first data to the point of persistence. The point of persistence may be the persistent memory itself or a persist buffer. The persist buffer may be a volatile or non-volatile buffer. One or more monitors may control access to data at memory addresses dependent upon a designated state of exclusivity.

A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing topological scheduling on a machine-learning accelerator having an array of tiles. One of the methods includes performing, at each time step of a plurality of time steps corresponding respectively to columns within each of a plurality of wide columns of the tile array, operations comprising: performing respective multiplications using tiles in a respective tile column for the time step, computing a respective output result for each respective tile column for the time step including computing a sum of results of the multiplications for the tile column, and storing the respective output result for the tile column in a particular output RAM having a location within the same tile column and on a row from which the output result will be read by a subsequent layer of the model.

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Disclosed herein is a persistent memory (PMEM)-based distributed memory object system, referred to as the PMEM DMO system, that provides affordable means of integrating low-latency PMEM spaces with other devices, including servers that do not directly support PMEM. One embodiment comprises providing a cluster of servers with PMEM storage (PMEM servers) and connecting the PMEM servers to a plurality of applications servers using a low-latency network, such as a remote direct memory access; background processes on each of the application servers are tasked to perform input/output operations for the application servers to locally materialize objects from and synchronize/persist objects to the remote PMEM spaces on the PMEM servers. Data materialized from the PMEM servers is stored to the local cache of the application server for use. Also disclosed are data eviction policies for clearing the local cache of the application servers to make space for new data read.