A GOA circuit includes GOA circuit units. Each of the GOA circuit units at each stage includes an input control module, an output control module, and a pull-down module. The pull-down module includes a first transistor, a second transistor, a third transistor, and a resistor. The GOA circuit unit uses fewer transistors and fewer capacitors. Therefore, the GOA circuit unit proposed by the present invention is beneficial for being used in displays with a narrow bezel. In addition, the GOA circuit unit omits a capacitor so power generated after the capacitor is charged is reduced. It provides a beneficiary effect of reducing power of the whole GOA circuit.

A display device of the disclosure includes a plurality of pixels and a driver. The driver unit makes scanning of pixels that belong to a plurality of pixel lines out of the plurality of pixels, in units of pixel line groups each of which is constituted by a predetermined number of the pixel lines, in a scanning order indicated by scanning ordinal numbers associated with the respective pixel line groups, to perform a write drive that includes writing a pixel voltage to each pixel. The scanning ordinal numbers are set to allow a sum of the scanning ordinal numbers of any two adjacent pixel line groups to approximate to a predetermined value.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

In a forward shift operation, a second input signal having a higher voltage than a voltage of a first input signal is input to a second gate terminal in a case that a first gate terminal of a first transistor is charged, and a fourth input signal having a higher voltage than a voltage of a third input signal is input to a third gate terminal in a case that the first gate terminal of the first transistor is discharged. In a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.

The present application provides a method and display apparatus for improving uniformity of displayed image, The method comprises inputting a first image signal to a display apparatus; compensating the first image signal in accordance with an image compensation data to obtain a third image signal, wherein the image compensation data is an amount of shift in a voltage of a common electrode of an array substrate of the display apparatus determined in accordance with a difference value between a grey level information of the first image signal and the grey level information of an original second image signal corresponding to the first image signal; and displaying the third image signal. Through the method above, the present invention effectively improves the uniformity of the displayed image without decreasing the displayed brightness of the image.

The present invention provides a panel signal control circuit, a display panel and a display device. The panel signal control circuit comprises: a PWM IC and a level shift IC, and the panel signal control circuit comprises further comprises: a Vin voltage divider circuit; one end of the Vin voltage divider circuit is coupled to an input port of an input working voltage Vin of the PWM IC, and the other end of the Vin voltage divider circuit is grounded; a voltage divider interface of the Vin voltage divider circuit is coupled to a pin a of the Level shift IC, and the pin a is a voltage monitor pin, and as the voltage of the pin a is lower than an activation voltage threshold, respective output clock CK pins of the Level shift IC output sync signals of an output working voltage VGH of the PWM IC.

Provided is an electro-optical device including a plurality of pixel electrodes arranged in a display region, a first transistor that captures a pulse supplied to a source node by using a clock signal supplied to a gate node and outputs the pulse from the drain node, a second transistor to which the pulse output from the drain node is input, and a capacitance element having one end coupled to the drain node and another end held at a predetermined potential. In the capacitance element, an interlayer insulating film is sandwiched between a first peripheral electrode formed of a same layer as the plurality of pixel electrodes and a wiring formed of a predetermined electrode layer, and the wiring includes a portion overlapping the second transistor in plan view.

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Power consumption of a display device is reduced by controlling power supplies in driving sections and in non-driving sections to be different.

A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.