Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. Each non-volatile memory cell is configured to store a plurality of bits of a plurality of logical pages including at least a first bit of a first logical page, a second bit of a second logical page and a third bit of a third logical page. The control circuits are configured to select a subset of the plurality of logical pages for reading, perform pre-read steps, and read a first and at least a second selected logical page of the subset without performing pre-read steps between reading the first and second selected logical pages.

A pipe latch circuit includes a data latch circuit configured to latch an input data based on an input control signal and output the latched input data as a latch data based on an output control signal, a sense amplification circuit configured to sense and amplify the latch data based on a sum output control signal, and a data driving circuit configured to drive an output data from the latch data based on the sum output control signal.

Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.

A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.