A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal. The drain of the first upper select transistor of the first cell is electrically coupled to the first output line and the drain of the first upper select transistor of the second cell is electrically coupled to the second output line.

Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

A charge pump apparatus includes a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit successively adjusts a code of a voltage regulation signal according to the output voltage, in order to control the second charge pump system to successively adjust the second boost voltage according to the voltage regulation signal.

A radiation detection system may include a mobile device having a flash memory. The device may monitor various characteristics of the flash memory to determine when damage to the flash memory has occurred from radiation exposure. The device may associate damage to the flash memory with a radiation dose, and determine a level of radiation to which the memory, and thus the device, has been exposed. The device also may determine a length of time and locations where the radiation exposure has occurred. If the device determines that the level of radiation exposure exceeds a threshold associated with a safe level of radiation exposure for a human user, the device may generate an alert to the user.

Examples of programming circuits and methods are disclosed. In one example, an adjustable programming circuit for generating a programming voltage is disclosed, the circuit comprising an operational amplifier comprising a first input terminal, a second input terminal, and an output terminal, the first input terminal receiving a reference voltage; a first switched capacitor network coupled between the second input terminal of the operational amplifier and the output terminal of the operational amplifier; and a second switched capacitor network coupled between an input voltage and the second input terminal of the operational amplifier; wherein the output terminal of the operational amplifier outputs a programming voltage that varies in response to a capacitance of the first switched capacitor network and a capacitance of the second switched capacitor network.

A semiconductor device includes a semiconductor substrate and a first memory cell disposed on the semiconductor substrate. The first memory cell includes a first write and erasure transistor, a first read transistor, and a first charge transfer reduction transistor. The first write and erasure transistor controls data writing and erasing. The first read transistor controls data reading. The first charge transfer reduction transistor reduces injection of an electric charge to the first write and erasure transistor and the first read transistor.

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate including a channel region; a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer; a control gate positioned above the floating gate and separated from the floating gate electrode by the inter-gate dielectric structure; the method including programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer; measuring over time a change in a threshold voltage of the flash memory cell; and determining the leakage current from the change in the threshold voltage.

A nonvolatile storage element includes a substrate; a gate region having a charge holding region and an insulator surrounding an entire surface of the charge holding region; a drain region formed in one of both sides of a lower portion of the gate region; and a source region formed in another one of both the sides. A halogen is distributed in the insulator to cover an entire surface of an upper surface of the charge holding region.

Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.