Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.

Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.

A method for implementing a neural network system in an integrated circuit includes presenting digital pulses to word line inputs of a matrix vector multiplier including a plurality of word lines, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line, each digital pulse having a pulse width proportional to an analog quantity. During a charge collection time frame charge collected on each of the summing bit lines from current flowing in the programmable Vt transistor is summed. During a pulse generating time frame digital pulses are generated having pulse widths proportional to the amount of charge that was collected on each summing bit line during the charge collection time frame.

Technologies for performing a quick reliability scan include, for a particular block of a set of blocks of different block types. Each block of the set of blocks includes pages of memory of a physical memory device. A subset of the pages of the block is identified. The block is scanned by scanning the subset of the plurality of pages of the block for a fold condition. A page of the subset of the plurality of pages is determined to have the fold condition. After the set of blocks has been scanned, the folding of the block that includes the page that has been determined to have the fold condition is requested.

A P layer 2 having a band shape is on an insulating substrate 1. An N.sup.+ layer 3a connected to a first source line SL1 and an N.sup.+ layer 3b connected to a first bit line are on respective sides of the P layer 2 in a first direction parallel to the insulating substrate. A first gate insulating layer 4a surrounds a portion of the P layer 2 connected to the N.sup.+ layer 3a, and a second gate insulating layer 4b surrounds the P layer 2 connected to the N.sup.+ layer 3b. A first gate conductor layer 5a connected to a first plate line and a second gate conductor layer 5b connected to a second plate line are isolated from each other and cover two respective side surfaces of the first gate insulating layer 4a in a second direction perpendicular to the first direction. A third gate conductor layer 5c connected to a first word line surrounds the second gate insulating layer 4b. These components constitute a dynamic flash memory.

In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that are partially etched such that the partially etched select gates are partially shaped as compared to the select gates of NAND strings that have not been etched. Host data is programmed to non-volatile memory cells that are connected to an edge word line and are on NAND strings having a complete shaped select gate. Host data is also programmed to non-volatile memory cells that are connected to non-edge word lines. However, host data is not programmed to non-volatile memory cells that are connected to the edge word line and are on NAND strings having a partial shaped select gate.

In a non-volatile memory, a block of NAND strings is divided into sub-blocks by etching the select gate layers between sub-blocks. This results in a subset of NAND strings (e.g., at the border of the sub-blocks) having select gates that are partially etched such that the partially etched select gates are partially shaped as compared to the select gates of NAND strings that have not been etched. Host data is programmed to non-volatile memory cells that are connected to an edge word line and are on NAND strings having a complete shaped select gate. Host data is also programmed to non-volatile memory cells that are connected to non-edge word lines. However, host data is not programmed to non-volatile memory cells that are connected to the edge word line and are on NAND strings having a partial shaped select gate.

An n.sup.+ layer 3a connected to a source line SL at both ends, an n.sup.+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.