A system includes a memory device with multiple memory dies and at least a spare memory die. A processing device is coupled to the memory device. The processing device is to track a value of a write counter representing a number of write operations performed at the multiple memory dies. The processing device is to activate the spare memory die in response to detection of a failure of a first memory die of the multiple memory dies. The processing device is to store an offset value of the write counter in response to the detection of the activation of the spare memory die, the offset value representing the value of the write counter upon activation of the first spare memory die.

A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.

Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

The present embodiments provides a memory repair solution finding device and method which find a fault by testing a memory and find a repair solution in parallel and dynamically reconfigure the stored fault information to minimize a repair solution searching time with an optimal repair rate.

Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.

A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

A memory system includes a memory device including a memory cell array including a plurality of memory cell groups, and a controller for selectively activating or inactivating one of the memory cell groups.