Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, determine that at least one of the memory regions is at or near end of life, and in response to the determination—send a notification to the host device that a logical memory capacity of the memory device will be reduced and then retire the at least one of the memory regions.

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, wherein the first logical memory capacity is less than the physical memory capacity, determine that at least one of the memory regions is at or near end of life, and in response to the determination, (1) retire the at least one of the memory regions and (2) reduce a logical memory capacity of the host device to a second logical memory capacity that is less than the first logical memory capacity.

A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

A first pool of blocks of a memory device is determined, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell. A second pool of blocks of the memory device is determined, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell. In response to detecting a failure associated with a particular block of the second pool of blocks, the particular block is added to the first pool of blocks.

The present disclosure relates to an electronic device. According to the present disclosure, a storage device includes a memory controller acquiring a valid address reflecting a bad block more quickly and a memory device including a plurality of memory devices each including a plurality of memory blocks included in each of a plurality of planes.

A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.

A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.

A memory system includes a memory device and a controller. The memory device includes a memory block configured to store target data. The controller is configured to maintain the target data in a write buffer until a program operation to the memory block succeeds, update a write cache tag regarding the target data when the program operation fails and a read only mode is entered, and read the target data from the write buffer based on the write cache tag when a read command regarding the target data is received.