A controller of a memory system performs a soft decoding without additional reads. The controller applies each of read voltages to cells to obtain a corresponding cell count and corresponding data, stores the obtained data, and processes the stored data. The controller determines a set of parameters, based on (i) the read voltages, (ii) cell counts corresponding to the read voltages and (iii) a non-negative regularization parameter. The controller estimates an optimal read voltage based on the set of parameters, generates log-likelihood ratio (LLR) values using the processed data and the optimal read voltage and performs soft decoding using the LLR values.

A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to manage the memory device using a cell level assignment with respect to a plurality of memory cell levels, determine a cell count for each of the cell levels associated with original data of the memory device that is to be accessed, predict an error rate from the cell counts, and selectively adjust the cell level assignment based on the error rate.

The present technology provides a method of operating a controller that controls a semiconductor memory device including a plurality of memory cells. The method of operating the controller includes controlling the semiconductor memory device to perform a read operation on selected memory cells among the plurality of memory cells by using a read voltage set including at least one read voltage, receiving read data from the semiconductor memory device, and changing at least one read voltage included in the read voltage set by counting, based on the read data, a number of memory cells each having a threshold voltage lower than the at least one read voltage included in the read voltage set.

A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

An electronic device is provided. A memory device controls a signal for setting a voltage level of a bit line. The memory device includes a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops for programming selected memory cells among the plurality of memory cells, and a sense signal controller configured to determine, during a program operation on a first memory cell among the selected memory cells, a bit line set-up time of a bit line coupled to the first memory cell based on at least one of a state of second memory cells adjacent to the first memory cell and a number of program loops performed on the first memory cell, the first memory cell having a threshold voltage higher than a pre-verify voltage and lower than a main verify voltage.

A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.

A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.

A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.