ARCHITECTURE AND METHOD FOR NAND MEMORY PROGRAMMING

Abstract

A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

Claims

1. A memory device, comprising: memory cells; and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

2. The memory device of claim 1, wherein the verification data comprises: inhibit information and first state failure verification information, wherein the first state failure verification information indicates the memory cells that fails a first state verification.

3. The memory device of claim 2, wherein the verification data further comprises inverted inhibit information, wherein the inverted inhibit information is configured to indicate unverified states of the memory cells that include a first state and remaining states subsequent to the first state.

4. The memory device of claim 2, wherein the first latch circuit is configured to store second state failure verification information, wherein the second state failure verification information indicates the memory cells that fails a second state verification.

5. The memory device of claim 1, further comprises a fourth latch circuit and a fifth latch circuit, coupled to the memory cells, wherein the third latch circuit is configured to store a first cell information of the program data, and the first cell information indicates a first bit of the one of the memory cells, the fourth latch circuit is configured to store second cell information of the program data, and the second cell information indicates a second bit of the one of the memory cells, and the fifth latch circuit is configured to store third cell information of the program data, and the third cell information indicates a third bit of the one of the memory cells.

6. The memory device of claim 1, wherein the second latch circuit is configured to store first state adjusted verification information comprising bit line information, wherein the first state adjusted verification information indicates which of the memory cells receive a first state adjusted verification voltage.

7. The memory device of claim 2, further comprising: control circuitry coupled to the memory cells, the first latch circuits, and the second latch circuits, and configured to: store the inhibit information to the first latch circuits and the second latch circuits; apply a first state programming voltage to the memory cells to program the memory cells to the first state; apply a first state verification voltage to the memory cells to perform a first state verification operation on the memory cells, the first state verification operation verifying first state threshold voltages of the memory cells based on a first target value and generating failure pattern data of the first state verification operation, the failure pattern data being stored to the second latch circuits and indicating the memory cells that passes the first state verification operation and the memory cells that fails the first state verification operation; and apply a first state adjusted verification voltage to the memory cells that fails the first state verification to perform a first state adjusted verification operation on the memory cells that fails the first state verification, the first state adjusted verification operation verifying the first state threshold voltages of the memory cells to which the first state adjusted verification voltage is applied.

8. The memory device of claim 7, wherein the control circuitry further comprises a verification state counter that is configured to: increment a counter value of the verification state counter in response to a failure rate of the failure pattern data being equal to or less than a second value, the counter value of the verification state counter indicating in which state the memory cells is being programmed, wherein the verification state counter is stored in the second latch circuit.

9. The memory device of claim 8, wherein the control circuitry is further configured to: apply a first state programming voltage to the memory cells to program the memory cells to the first state based on the counter value of the verification state counter being less than a first value.

10. The memory device of claim 9, wherein the control circuitry is further configured to: determine an initial first state programming voltage according to the inhibit information stored in the first latch circuits and the counter value; replace the inhibit information with initial adjusted verification information in the first latch circuits, the initial adjusted verification information indicating which of the memory cells receive a previous adjusted verification voltage in a previous adjusted verification operation prior to the first state adjusted verification operation; determine the first state programming voltage based on the initial first state programming voltage and the initial adjusted verification information; and apply the first state programming voltage to the memory cells for programing the memory cells to the first state.

11. The memory device of claim 10, wherein the control circuitry is further configured to: invert the inhibit information in the first latch circuits, wherein inverted inhibit information indicates unverified states of the memory cells that include the first state and remaining states subsequent to the first state; and apply the first state verification voltage to the memory cells to perform the first state verification operation, the first state verification voltage being determined according to the inverted inhibit information stored in the first latch circuits.

12. The memory device of claim 11, further comprises verification circuits, wherein: each of the verification circuits is coupled to a respective first latch circuit and a respective second latch circuit, the verification circuits are configured to verify whether the first state threshold voltages of the memory cells meet a first target value, and the failure pattern data of the first state verification operation is stored to the second latch circuits through the verification circuits.

13. A memory device, comprising: a memory array comprising memory cells; a page buffer comprising a first latch circuit, a second latch circuit, and a third latch circuit, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data; and a control logic configured to control access to the memory array in response to commands and generate status information for an external processor.

14. The memory device of claim 13, wherein the first latch circuit is further configured to store inverted inhibit information, wherein the inverted inhibit information is configured to indicate unverified states of the memory cells that include a first state and remaining states subsequent to the first state.

15. The memory device of claim 13, wherein the page buffer comprises a fourth latch circuit and a fifth latch circuit, wherein the third latch circuit is configured to store first cell information of the program data, and the first cell information of the memory cells indicates a first bit of one of the memory cells, the fourth latch circuit is configured to store second cell information of the program data, and the second cell information of the memory cells indicates a second bit of the one of the memory cells, the fifth latch circuit is configured to store third cell information of the program data, and the third cell information of the memory cells indicates a third bit of the one of the memory cells.

16. The memory device of claim 13, wherein the first latch circuit is configured to: store second state failure verification information, and the second state failure verification information indicates the memory cells that fails a second state verification.

17. The memory device of claim 13, wherein the second latch circuit is configured to store first state adjusted verification information comprising bit line information, wherein the first state adjusted verification information indicates which of the memory cells receive a first state adjusted verification voltage.

18. A method of programming a memory device that includes memory cells, comprising: storing inhibit information to first latch circuits and second latch circuits during a verification operation; inverting the inhibit information in the first latch circuits to form inverted inhibit information in the first latch circuits, wherein the inverted inhibit information indicates unverified states of the memory cells that include a first state and remaining states subsequent to the first state during the verification operation; storing first state failure verification information in the first latch circuits, wherein the first state failure verification information indicates the memory cells that fails a first state verification during the verification operation; and storing failure pattern data in the second latch circuits during the verification operation, wherein the failure pattern data indicates which of the memory cells fails the verification operation.

19. The method of claim 18, further comprising: storing first state adjusted verification information in the second latch circuits, wherein the first state adjusted verification information comprises bit line information, wherein the first state adjusted verification information indicates which of the memory cells receive a first state adjusted verification voltage.

20. The method of claim 19, further comprising: storing second state failure verification information in the first latch circuits, wherein the second state failure verification information indicates the memory cells that fails a second state verification.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Aspects of the present disclosure can be understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be increased or reduced for clarity of discussion.

[0047] FIG. 1 is a schematic diagram of a 3D-NAND memory device, in accordance with exemplary embodiments of the disclosure.

[0048] FIG. 2 is a cross-sectional view of a 3D-NAND memory device, in accordance with exemplary embodiments of the disclosure.

[0049] FIG. 3 is a schematic diagram of a NAND memory cell string, in accordance with exemplary embodiments of the disclosure.

[0050] FIG. 4A is a schematic view of data storage in a triple level cell (TLC) of a 3D-NAND device, in accordance with exemplary embodiments of the disclosure.

[0051] FIG. 4B is a schematic view of data storage in a quadruple-level cell (QLC) of a 3D-NAND device, in accordance with exemplary embodiments of the disclosure.

[0052] FIG. 5A is an exemplary block schematic of a circuit of a 3D-NAND, in accordance with exemplary embodiments of the disclosure.

[0053] FIG. 5B is an exemplary block schematic of a circuit of a 3D-NAND, in accordance with exemplary embodiments of the disclosure.

[0054] FIG. 6 is a flow chart diagram of a method for memory programming, in accordance with exemplary embodiments of the disclosure.

[0055] FIGS. 7-13 are schematic diagrams of various latch states when programming a memory, in accordance with exemplary embodiments of the disclosure.

[0056] FIG. 14 is a block schematic of an electronic system, in accordance with exemplary embodiments of the disclosure.

DETAILED DESCRIPTION

[0057] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features may be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

[0058] Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0059] A 3D-NAND device can include a plurality of planes. Each of the planes can include a plurality of blocks. FIG. 1 is an exemplary embodiment of a 3D-NAND device 100 (or device 100). As shown in FIG. 1, the device 100 can include planes 102 and 104. Each of the planes 102 and 104 can include two respective blocks. For example, the plane 102 can include two blocks 106 and 108, and the plane 104 can include two blocks 110 and 112. Further, each of the blocks can include a plurality of memory cell strings, where memory cells are disposed sequentially and in series over a substrate along a height direction of the device 100. It should be noted that FIG. 1 is merely an example, and the device 100 can include any number of planes, and each of the planes can include any number of blocks according to the device designs. In the device 100, each of the planes can be coupled to a respective cache circuit, such as a dynamic data cache (DDC), or a static page buffer (SPB). For example, the block 106 can be coupled to a cache circuit 114 and the block 108 can be coupled to a cache circuit 116. The cache circuit can include sense amplifiers that are coupled to bit lines and configured to sense signals during the operation of the 3D-NAND device 100. The cache circuit can include a plurality of page buffers. Each of the page buffers can be coupled to a respective bit line, and includes a plurality of latches (or latch circuits). The page buffers are configured to temporarily hold data when the 3D-NAND device 100 is operated. For example, when memory cells of the 3D-NAND device are triple level cells (TLCs), each of the page buffers can include six latches. The device 100 can also include periphery circuits 122 that can include decoder circuits, driver circuits, charge circuits, and other circuits to operate the memory cells.

[0060] In the device 100, each of the blocks can include staircase regions and array regions that are formed in a stack of word line layers and insulating layers. FIG. 2 is an exemplary embodiment of the block 106 of the device 100. As shown in FIG. 2, the block 106 can include an array region 200A and staircase regions 200B-200C. The array region 200A can be arranged between the staircase regions 200B-200C, and formed in a stack of alternating word line layers 12a-12p and insulating layers 14a-14q over a substrate 10. The word line layers 12a-12p can include one or more bottom select gate (BSG) layers, gate layers (or word line layers), and one or more top select gate (TSG) layers that are arranged sequentially over the substrate 10. For example, the word line layers 12o-12p can be the BSG layers, and the word line layers 12a-12b can be the TSG layers in the device 100. The array region 200A can include a plurality of channel structures 18. Each of the channel structures 18 can extend through the stack and be coupled to the word line layers 12a-12p to form a respective vertical NAND memory cell string. The vertical NAND memory cell string can include one or more bottom select transistors (BSTs), a plurality of memory cells (MCs), and one or more top select transistors (TSTs) that are disposed sequentially and in series over the substrate along a height direction (e.g., Z direction) of the substrate 10. The one or more BSTs can be formed of the channel structure and the one or more BSG layers, the MCs can be formed of the channel structure and the word line layers, and the one or more TSTs can be formed of the channel structure and the one or more TSG layers.

[0061] In the device 100, each of the memory cells can store one or more logic bits, according to the device designs. For example, the memory cells can be single level cells (SLCs), multiple level cells (MLCs), triple level cells (TLCs), or quadruple-level cells (QLCs). Accordingly, each of the memory cells can store one logic bit, two logic bits, or three logic bits.

[0062] Still referring to FIG. 2, the word line layers 12a-12p can be formed in a stair-cased configuration in the staircase regions 200A-200B, and a plurality of word line contacts 22 can be formed along the height direction and coupled to the word line layers 12a-12p. Thus, gate voltages can be applied on gates of the memory cells through the word line contact 22 that is coupled to the word line layers 12a-12p.

[0063] In addition, each of the channel structures can further be coupled to a respective bit line (or bit line circuit). In some embodiments, the bit line can be connected to a top channel contact 19 of the channel structure 18, and configured to apply a bias voltage when operating the channel structure, such as programming, erasing, or reading the channel structure. The device 100 can have a plurality of slit structures (or gate line slit structures). For example, two slit structures 20a-20b are included in FIG. 2. The slit structures 20a-20b can be made of conductive materials and positioned on array common source (ACS) regions 16 to serve as contacts. The ACS regions are formed in the substrate 10 to serve as common sources of the device 100.

[0064] FIG. 3 is a schematic view of a NAND memory cell string (or string) 300 that can be formed in the device 100. As shown in FIG. 3, the string 300 can include a bottom select transistor (BST) 302, a plurality of memory cells (MCs) 304, and a top select transistor (TST) 306 that are disposed sequentially and in series over the substrate along the height direction (e.g., Z direction) of the substrate 10. The string 300 can be coupled to a bit line 308 through a drain terminal of the TST 306, and coupled to an ACS 310 through a source terminal of the BST 302. During the operation of the device 100, appropriate voltages can be applied to the bit line 308, the gate of the TST 306 through the TSG layer, the gates of the MCs 304 through the word line (WL) layers, the gate of the BST 302 through the BSG layer, and the ACS 310 through the slit structure (e.g., 20a or 20b).

[0065] As mentioned above, the memory cells can be single level cells, multiple level cells, triple level cells, or quad level cells that can store single logic bit, two logic bits, three logic bits, or four logic bits respectively. FIG. 4A is a schematic view of data storage in a TLC of the 3D-NAND device. As shown in FIG. 4A, the TLC can have eight threshold voltages Vt0-Vt7 (or eight levels LV0-LV7), and each of the eight threshold voltages Vt0-Vt7 can represent three corresponding logic bits. For example, the first threshold voltage (or first level LV0) Vt0 corresponds to logic bits 000, and the second threshold voltage (or second level LV1) Vt1 corresponds to logic bits 100. Thus, by adjusting a threshold voltage of the TLC to a target value (or target threshold voltage), the TLC can be programmed (or written) with corresponding logic bits. When the programming operation of the TLC is completed, a subsequent verification operation can be performed to verify whether the threshold voltage of the TLC meets the target value. The logic bits stored in the TLC can further be divided into three logic pages that are a first cell, a second cell and a third cell. For example, logic bits 100 of the second level LV1 of the TLC can further be stored in the first cell, the second cell, and the third cell, where the logic bit 1 can be stored in the third cell, the first logic bit 0 can be stored in the second cell, and the second logic bit 0 can be stored in the first cell. Information in each of the logic pages (e.g., first cell information, second cell information, and third cell information) can represent a respective entity, such as a song, or a picture. In some implementations, these cell information can be referred as program data. In some embodiments, information in each of the logic pages can be temporally stored in a corresponding latch during the programming operation. In implementations of TLC, a minimum of 5 latches are needed.

[0066] FIG. 4B is a schematic view of data storage in a QLC of the 3D-NAND device. As shown in FIG. 4B, the QLC can have 16 threshold voltages Vt0-Vt15 (or 16 levels LV0-LV15), and each of the 16 threshold voltages Vt0-Vt15 can represent four corresponding logic bits. For example, the first threshold voltage (or first level LV0) Vt0 corresponds to logic bits 0000, and the second threshold voltage (or second level LV1) Vt1 corresponds to logic bits 1000. Thus, by adjusting a threshold voltage of the QLC to a target value (or target threshold voltage), the QLC can be programmed (or written) with corresponding logic bits. When the programming operation of the QLC is completed, a subsequent verification operation can be performed to verify whether the threshold voltage of the QLC meets the target value. The logic bits stored in the QLC can further be divided into four logic pages that are a first cell, a second cell, a third cell, and an extra page. For example, logic bits 1000 of the second level LV1 of the QLC can further be stored in the first cell, the second cell, and the third cell, where the logic bit 1 can be stored in the extra page, the first logic bit 0 can be stored in the third cell, the second logic bit 0 can be stored in the second cell, and the third logic bit 0 can be stored in the first cell. Information in each of the logic pages (e.g., first cell information, second cell information, third cell information, and fourth cell information) can represent a respective entity, such as a song, or a picture. In some embodiments, information in each of the logic pages can be temporally stored in a corresponding latch during the programming operation. In implementations of QLC, a minimum of 6 latches are needed.

[0067] When the 3D-NAND device is programmed according to related methods, three latches of the page buffer can be used to store the original data (or processed data) throughout the entire programming operation. In addition, one specific latch (also referred to as an inhibit latch) can be reserved to store inhibit information, one latch can be used for sensing/programming, and one latch can be applied for storing 3BL (3 bit line) information. In the disclosure, a sensing scheme, which is called as non-inhibit verification, is provided for the programming operation of the 3D-NAND device. In the non-inhibit verification, a page buffer that includes five latches can be applied. Accordingly, a number of latches, such as the six latches applied in related methods, can be reduced. In addition, in the non-inhibit verification, less page buffer operations can be applied when verification states are switched.

[0068] FIG. 5A is an exemplary block schematic of a circuit 500 that is utilized in the programming operation. As shown in FIG. 5A, the circuit 500 can include a page buffer 500A. The page buffer 500A can include a DS latch (or first latch) 502 configured to store verification data including inhibit information and verification information from the verification operation, a DL latch (or second latch) 504 configured to store inhibit information and 3BL information (or adjusted verification information from an adjusted verification operation), a D1 latch (or third latch) 506 configured to store first cell information of the memory cells during the programming operation, a D2 latch (or fourth latch) 508 configured to store second cell information of the memory cells, and a DC latch (or fifth latch) 510 configured to store third cell information of the memory cells. The DS latch 502, the DL latch 504, the D1 latch 506, the D2 latch 508, and the DC latch 510 can further be coupled to each other and share data with each other. In some embodiments, the latches in the page buffer 500A can be formed of cross-coupled logic inverters. In implementations of SLC, MLC, TLC, or QLC, a data latch (e.g., third latch 506) stores the program data. The program data may include first cell information of the memory cells, second cell information of the memory cells, third cell information of the memory cells, or fourth cell information of the memory cells depending on different architectures. These cell information can be stored in only one data latch or can be stored in separated latches such as D2 latch, D3 latch, D4 latch, etc.

[0069] The circuit 500 can also include a bit line (BL) bias circuit 512 that is coupled to the DS latch 502. The BL bias circuit 512 can further be coupled to a bit line (BL) 516 and apply bias voltage to the BL 516 according to the inhibit information stored in the DS latch 502. During the programming operation, a programming voltage can be applied to the BL 516 through the BL bias circuit 512. The programming voltage can further be applied to the memory cells through the BL 516 for programming the memory cells. During the verification operation, a verification voltage can be applied to the BL 516 through the BL bias circuit 512. The verification voltage can further be applied to the memory cells through the BL 516 for the verification operation. The circuit 500 can also include a verification circuit 514, such as a sense amplifier, that is coupled to the BL 516, the DS latch 502, and the DL latch 504. The verification circuit 514 can be configured to read the memory cells during the verification operation to verify whether the threshold voltages of the memory cells meet a target value. If the threshold voltages of the memory cells meet the target value, it indicates that the memory cells pass the verification operation. If the threshold voltages of the memory cells do not meet the target value, it indicates that the memory cells fail the verification operation. When the threshold voltages of the memory cells do not meet the target value, an adjusted verification voltage can be applied to the memory cells through the BL 516 to verify whether the threshold voltages of the memory cells can meet an adjusted value. The verification data includes a result of verifying during a verification operation. During the verification operation, data stored in the memory cell or a threshold voltage of the memory cell may be sensed. During a program operation, the first latch may be utilized for applying a programming voltage or an inhibit voltage to the bit line according to the verification data in a previous verification operation.

[0070] The verification circuit 514 can further generate a failure pattern data (also referred to as verify failure counter (VFC)) that indicates which of the memory cells fails the verification operation. The verification circuit 514 can further transmit verification information to the DL latch 504. The circuit 500 can also include a verification level counter (not shown) that is configured to increment a counter value, for example increase a counter value of the verification level counter by one, in response to a failure rate of the failure pattern data being equal to or less than a standard value, such as 10%. The counter value of the verification level counter can indicate in which level the memory cells are programmed.

[0071] It should be noted that the 3D-NAND device (e.g., device 100) can include a plurality of circuits 500 that are arranged in the cache circuits (e.g., 114, 116), and each of the circuits 500 can be coupled to a respective bit line of the 3D-NAND device and be utilized in the programming operation.

[0072] FIG. 5B is an exemplary block schematic of a circuit 550 of a QLC architecture of the 3D-NAND device that is utilized in the programming operation. For the ease of description to describe FIG. 5B, the same reference numerals and/or letters in FIG. 5B represent the same described in FIG. 5A. As shown in FIG. 5B, the circuit 550 can further include a D3 latch (or sixth latch) 512 configured to store fourth cell information of the memory cells. The DS latch 502, the DL latch 504, the D1 latch 506, the D2 latch 508, the D3 latch 512, and the DC latch 510 can further be coupled to each other and share data with each other. In some embodiments, the latches in the page buffer 500A can be formed of cross-coupled logic inverters.

[0073] FIG. 6 is a flow chart diagram of a method 600 for memory programming, in accordance with exemplary embodiments of the disclosure. As shown in FIG. 6, the method 600 can include program pulse operation 600A that is configured to program memory cells of a 3D NAND device (e.g., device 100), and program verification operation 600B that is configured to verify whether the memory cells are programmed to target threshold voltages. As shown in FIG. 6, the method 600 can begin at step S604, where a preparation can be performed. In the preparation, the memory cells can be erased to receive new data, and inhibit information can be set (or stored) in first latches (e.g., DS latch 502) and second latches (e.g., DL latch 504). The inhibit information can be formed of logic 1 and logic 0, where the logic 1 indicates not to program the unselected string of the memory cells, and the logic 0 indicates to program the selected strings of the memory cells. In particular, the bit line voltages applied in respective bit lines may vary depending on the inhibit information. That is, the bit line voltages may include programming voltages of selected strings and inhibit voltages of unselected strings. It is noted that whether the inhibit voltages or the programming voltages are applied correspond to the inhibit information mentioned above. For instance, the inhibit voltage may be 5 V and the programming voltage may be 20 V. The bit lines of selected strings will be provided with programming voltages and the bit lines of unselected strings will be provided with inhibit voltages. And whether it will provide the bit lines with inhibit voltages or programming voltages are determined by the inhibit information stored in latches mentioned above. That is, if the logic of the inhibit information is 1, the inhibit voltage is applied to the respective bit line of the unselected string, and if the logic of the inhibit information is 0, the programming voltage is applied to the respective bit line of the selected string.

[0074] The method 600 can then proceed to step S606 which is a first step of the program pulse operation 600A. At step S606, an initial first state programming voltage can be determined according to the inhibit information set in the first latches (e.g., DS latch 502) and the counter value of the verification state counter. It is noted that the inhibit information set in the first latches may change dynamically and will be updated according to respective state adjusted verification in real time. In an exemplary embodiment of the method 600, the first state can be the third level LV2 of the memory cells, and thus the counter value of the verification state counter is two. The method 600 can then proceed to step S608 which is a second step of the program pulse operation 600A. At step S608, the inhibit information in the first latches (e.g., DS latch 502) can subsequently be replaced with initial adjusted verification information (3BL information) that was stored in the second latches (e.g., DL latch 504), where the initial adjusted verification information indicates which of the memory cells receive a previous adjusted verification voltage in a previous adjusted verification operation from a prior state (e.g. the second level LV1) to the first state (e.g., the third level LV2). A first state programming voltage can then be determined based on the initial first state programming voltage and the initial adjusted verification information, and applied to the data line (e.g., the word line, or bit line) of the memory cells for programing the memory cells to the first state (e.g., LV2).

[0075] The method 600 can proceed to step S610 to start the program verification operation 600B. At step S610, a first state verification voltage can be applied to the data lines of the memory cells to perform a first state verification (or a first state verification operation) on the memory cells, where the first state verification can verify first state threshold voltages of the memory cells based on a first target value and further generate failure pattern data (or VFC) of the first state verification. In an exemplary embodiment of FIG. 6, the first state is the third level LV2 of the memory cells, and the first state threshold voltages are accordingly Vt2. The failure pattern data can be set (transmitted, stored, or saved) to the second latch circuits (e.g., DL latch 504) and indicate a first portion of the memory cells that passes the first state verification and a second portion of the memory cells that fails the first state verification. In some embodiments, before the first state verification, the inhibit information in the first latch circuits can be inverted, and the inverted inhibit information indicates unverified states of the memory cells that include the first state (e.g., the third level LV2) and remaining states subsequent to the first states (e.g., LV3-LV7). In some embodiments, first state failure verification information can be added to the first latch circuits (e.g., DS latch 502), where the first state failure verification information indicates the second portion of the memory cells that fails the first state verification.

[0076] At step S612, failure pattern data can be counted to calculate a failure rate of the failure pattern data.

[0077] At step S614, a first state adjusted verification voltage can be applied to the data lines of the second portion of the memory cells that fails the first state verification to perform a first state adjusted verification (or a first state adjusted verification operation) on the second portion of the memory cells. In some embodiments, the inhibit information and first state adjusted verification information (or 3BL information) can be set to the second latch circuits. The first state adjusted verification information indicates which of the memory cells receive the first state adjusted verification voltage.

[0078] At step S616, a determination can be made based on failure rate of the failure pattern data. In response to the determination that the failure rate of the failure pattern data is equal to or less than a standard value (i.e., Pass at step S616), the method 600 can proceed to S618, where the counter value of the verification state counter can be increased by one, and then proceed to step S620. In response to the determination that the failure rate of the failure pattern data is larger than the standard value (i.e., Fail at step S616), the method 600 proceeds to step S620 directly.

[0079] At step S620, a second state verification voltage can be applied to the data lines of the memory cells to perform a second state verification (or second state verification operation) on the memory cells to verify a second state threshold voltage of the memory cells based on a second target value. In an exemplary embodiment of FIG. 6, when the first state is LV2, the second state is thus LV3, and the second state threshold voltage is accordingly Vt3. At step S622, a second state adjusted verification voltage can be applied to the data lines of a portion of the memory cells that fails the second state verification to perform a second state adjusted verification (or a second state adjusted verification operation) on the portion of the memory cells that fails the second state verification. As shown in steps S624 and S626, the verification operation and adjusted verification operation can be repeated for remaining states (e.g., LV4-LV7) of the memory cells until the verification and adjusted verification are completed for a last state (e.g., LV7). In some embodiments, failure verification information for the first state (e.g., LV2) and the states (e.g., LV3-LV7) subsequent to the first state can be set to the first latch circuits (e.g., DS latch 502), and adjusted verification information for the first state and the states subsequent to the first state can be set to the second latch circuits (e.g., DL latch 504).

[0080] The method 600 then proceeds to step S628, where a determination can be made to determine whether the counter value of the verification state counter is equal to the threshold value (e.g., eight) or less than the threshold value. As mentioned above, the counter value of the verification state counter indicates which state of the memory cells is to be programmed and verified. When the counter value of the verification state counter is equal to eight (e.g., Yes at S628), it indicates that the first state that is programmed and verified is the eighth level LV7 of the memory cells, and the eighth level LV7 is also successfully programmed. Thus the method 600 proceeds to step S699 because all levels (LV0-LV7) of the memory cells are programmed successfully. When the counter value of the verification state counter is less than eight (e.g., No at S628), it indicates that the first state is not the eighth level LV7 of the memory cells, and the method 600 needs to proceed to program and verify a next state that is indicated by the counter value of the verification state counter. For example, when the counter value of the verification state counter is three, the next state that needs to be programmed and verified is the fourth level LV3 of the memory cells.

[0081] As shown in S628, in response to the counter value being less than eight, the memory cells are programmed and verified for the next state. In an embodiment, the next state is still the first state in response to the counter value of the verification state counter being unchanged. In another embodiment, the next state is a subsequent state to the first state in response to the counter value of the verification state counter being increased by one at step S618. In order to program the next state of the memory cells, an initial programming voltage is determined according to the inhibit information set in the first latch circuits. Further, the inhibit information in the first latch circuits can be replaced with adjusted verification information in the first latch circuits. The adjusted verification information indicates which of the memory cells receive the first state adjusted verification voltage in the first state adjusted verification operation. A programming voltage thus can be determined based on the initial programming voltage and the adjusted verification information, and the programming voltage can be applied on the data lines of the memory cells to program the memory cells in the subsequent state (e.g., LV3) to the first state (e.g., LV2).

[0082] Table 1 shows a relationship of a verification level and verification content when the programming operation and the verification operation begin at the second level (e.g., LV1) of the memory cells.

TABLE-US-00001 TABLE 1 a relationship of a verification level and verification content Verifi LV1 LV2 LV3 LV4 LV5 LV6 LV7 cation level Verifi LV1~ LV1 LV1 (LV1~ (LV 1 ~ (LV 1 ~ (LV1~ cation LV7 Fail+ Fail+ LV3) LV4) LV5) LV6) Content LV2~ LV LV2 Fail+ Fail+ Fail+ Fail+ 7 Fail+ LV4~LV LV5~ LV6~ LV7 LV3~ 7 LV7 LV7 LV7

[0083] As shown in Table 1, when the second level (LV1) is a first state that is programmed and verified, the verification operation can verify the second level (LV1) to the eighth level (LV7). For a remaining state to the first state, the verification operation can verify the memory cells that fail in the previous states of the remaining state again in the previous states, and the memory cells from the remaining state to a last state (e.g., the eighth level LV7). For example, when the third level (e.g., LV2) is programmed and verified, the verification operation can verify memory cells that fail in the second level (e.g., LV1 fail) again in the second level (e.g., LV1), and continuously verify the memory cells from the remaining state, e.g., the third level (e.g., LV2) to the last level (e.g., LV7) without stopping the verification process. When the fourth level (e.g., LV3) is programmed and verified, the verification operation can verify memory cells that fail in the second level (e.g., LV1 fail) again in the second level (e.g., LV1), the memory cells that fail in the third level (e.g., LV2 fail) again in the third level (e.g., LV2), and the memory cells from the fourth level (e.g., LV3) to the eighth level (e.g., LV7).

[0084] FIGS. 7-13 are schematic diagrams of various latch states when programming a 3D-NAND memory device based on the method described above. As mentioned in FIG. 6, in order to program the 3D-NAND device, a preparation operation (e.g., S604 in FIG. 6) can be applied first. Subsequently, a programming operation (e.g., 600A in FIG. 6) can be applied to program (or write) the memory cells of the 3D-NAND device. Further, a verification operation (e.g., 600B in FIG. 6) can be applied to verify whether the memory cells are programmed successfully. FIG. 7 shows the latch states of the latches when a preparation operation (e.g., S604) is performed. As mentioned above, the 3D-NAND device can include memory cells that are formed of a plurality of vertical NAND memory cell strings. Each of the vertical NAND memory cell strings can be coupled to a respective bit line, and the bit line can further be coupled to a respective page buffer that include latches as shown in FIGS. 5A and 5B. In the preparation operation, the memory cells can receive to-be-programmed data, and inhibit information can be set (stored or saved) in DS latches (e.g., DS latch 502) and DL latches (e.g., DL latch 504). The inhibit information can be indicated by logic 1 and logic 0. For example, the logic 1 indicates that the memory cells are not to be programmed, and the logic 0 indicates that the memory cells are to be programmed. In addition, user data that is programmed in the memory cells can be stored in D1 latches, D2 latches, and DC latches. The D1 latches can save first cell information of the memory cells, the D2 latches can save second cell information of the memory cells, and the DC latches can save third cell information of the memory cells. When the preparation operation (e.g., S604 in FIG. 6) is completed, a program pulse (or programming voltage) can be applied to gates of the memory cells through BL bias circuits (e.g., BL bias circuit 512) by applying a WL voltage of selected word lines of the memory cells to program the memory cells that can be shown in program pulse 600A of FIG. 6. For example, the memory cells can be programmed to a first state. In an exemplary embodiment of FIG. 7, the first state is the third level LV2 of the memory cells.

[0085] FIG. 8 shows the latch states of the latches before the first state verification operation (e.g., S610 in FIG. 6) is performed. As shown in FIG. 8, the inhibit information in the DS latches can be inverted, where the inverted inhibit information (e.g., ˜inhibit information) can indicate unverified states of the memory cells. In an exemplary embodiment of FIG. 8, the inverted inhibit information indicates that the first state to be verified is the third level LV2 of the memory cells. In addition, the inverted inhibit information indicates that remaining states subsequent to the first state are LV3-LV7, and the first level LV0 and the second level LV1 of the memory cells pass the verification operation. Thus, ˜inhibit information can also be defined as ˜(LV0|LV1) (i.e., not LV0 or not LV1).

[0086] FIG. 9 shows the latch states of the latches when the first state verification operation (e.g., S610 in FIG. 6) is performed on the memory cells, where a first state verification voltage can be applied to the data lines (e.g., BL 516) of the memory cells and further be coupled to the gates of the memory cells in which a WL voltage is applied to the gates of the selected WLs of the memory cells to perform the first state verification operation (or first state verification). The verification result will be collected via the data lines (bit lines) of the memory cells coupled to the sense amplifier. The first state verification verifies whether first state threshold voltages of the memory cells meet the first target value (e.g., Vt2) when LV2 is the first state. The first state verification voltage can be a pulsed voltage signal that has an intensity close to the first target value. If the memory cells are turned on under the first state verification voltage, it can indicate that the threshold voltages of the memory cells do not meet the first target value and fail the first state verification. If the memory cells are not turned on under the first state verification voltage, it can indicate that the threshold voltages of the memory cells meet the first target value and pass the first state verification. In addition, verify failure counter (VFC) of the first state verification can be generated and set (saved, stored, or provided) to the DL latches (e.g., 504). The verify failure counter can include failure pattern data and indicate a first portion of the memory cells that passes the first state verification and a second portion of the memory cells that fails the first state verification. Further, first state failure verification information (e.g., 1st state PV pass) can be added to the DS latches. The first state failure verification information indicates the second portion of the memory cells that fails the first state verification.

[0087] FIG. 10 shows the latch states of the latches when a first state adjusted verification (e.g., S614 in FIG. 6) is performed, where a first state adjusted verification voltage can be applied to the data lines of the second portion of the memory cells that fails the first state verification to perform the first state adjusted verification on the second portion of the memory cells. In some embodiments, an intensity of the first state adjusted verification voltage can be set lower than the first state verification voltage. The first state adjusted verification voltage can be obtained by subtracting a delta voltage from the first state verification voltage. The delta voltage can be less than 1 volt, and can be named as a 3BL bias. Thus, the first state adjusted verification can also be referred to as the first state 3BL or first state 3BL verification. The first state adjusted verification voltage can verify whether the first state threshold voltages of the second portion of the memory cells can meet a first adjusted target value that is lower than the first target value. Further, the inhibit information and first state adjusted verification information (or 1st state 3BL information) that is obtained from the first state adjusted verification can be set to the DL latches (e.g., 504), where the first state adjusted verification information indicates which of the memory cells receive the first state adjusted verification voltage, and the inhibit information indicates the verified states (e.g., the first level LV0 and the second level LV1).

[0088] It should be noted that, as shown in S616 and S618 of FIG. 6, when the first state adjusted verification is completed, the counter value of the verification state counter can be incremented, for example increased by one, in response to a failure rate of the failure pattern data (VFC) being equal to or less than a standard value. When the failure rate of the failure pattern data is equal to or less than the standard value, it indicates that the memory cells are programmed successfully for the first state (e.g., the third level LV2).

[0089] FIG. 11 shows the latch states of the latches when the remaining states (e.g., from the fourth level to the eighth level LV3-LV7) subsequent to the first state (e.g., LV2) are verified sequentially that can be shown in S620-S626 in FIG. 6. Similar to the first state, each of the remaining states can receive a corresponding verification and a corresponding adjusted verification. In addition, failure verification information for each of the remaining states can be set to the DS latches, and adjusted verification information for each of the remaining states can be set to the DL latches.

[0090] For example, a second state verification voltage can be applied to the data lines of the memory cells and a second state verification can be performed on the memory cells to verify a second state threshold voltage (e.g., Vt3) of the memory cells based on a second target value. Subsequently, a second state adjusted verification voltage can be applied to the data lines of a third portion of the memory cells that fails the second state verification and the second state adjusted verification can be applied on the third portion of the memory cells that fails the second state verification. In addition, second state failure verification information (e.g., ˜2nd state PV pass) can be added to the DS latches, where the second state failure verification information is obtained from the second state verification and indicates the third portion of the memory cells that fails the second state verification. Further, second state adjusted verification information (e.g., 2nd state 3BL) can be added to the DL latch circuits, where the second state adjusted verification information indicates which of the memory cells receive the second state adjusted verification voltage.

[0091] As shown in FIG. 11, when the remaining states (e.g., from the fourth level to the eighth level LV3-LV7 of the memory cells) are verified sequentially, the inverted inhibit information and the failure verification information for all verified states (e.g., ˜(inhibit information of all levels|1st|2nd| . . . | last state PV pass) can be set to the DS latches, and the inhibit information and the adjusted verification information (e.g., inhibit information of all levels|1st|2nd| . . . |last state 3BL) for all verified states can be set to the DL latches. When the remaining states are all verified, it indicates that the memory cells are programmed to the first state (e.g., LV2).

[0092] In FIG. 12, the inverted inhibit information and the failure verification information for all verified states (e.g., ˜(inhibit information|1st|2nd| . . . |last state PV pass) that is set in the DS latches can be inverted to form the inhibit information and pass verification information for all verified states. Accordingly, the inhibit information and the pass verification information for all verified states is set (or stored) to the DS latches. In addition, whether the counter value of the verification state counter is greater than or equal to the threshold value can be determined. In an exemplary embodiment of FIG. 12, the threshold value can be eight, which indicates that the memory cells have eight levels (e.g., LV0-LV7). When the counter value of the verification state counter is eight, it indicates that the eighth level (e.g., LV7) of the memory cells passes the verification operation. In response to the determination that the counter value of the verification state counter is less than the threshold value, in an embodiment, the memory cells can be programmed and verified for the first state (e.g., LV2) again in response to the counter value of the verification state counter being unchanged. The memory cells can be programmed and verified for a subsequent state (e.g., LV3) to the first state in response to the counter value of the verification state counter being incremented (e.g., increased by one).

[0093] FIG. 13 shows the latch states of the latches when the memory cells are programmed for a next state according to the counter value of the verification level counter. As mentioned above, when the counter value of the verification state counter is not changed after the first state verification, the next state is still the first state (e.g., LV2) and the memory cells are programmed for the first state again. When the counter value of the verification level counter is changed after the first state verification, the next state is a subsequent state (e.g., LV3) to the first state (e.g., LV2) and the memory cells are programmed for the subsequent state. In order to program the next state, an initial programming voltage can be determined according to the inhibit information set in the DS latches. Further, the inhibit information can be replaced with the adjusted verification information (e.g., inhibit information|1st|2nd| . . . |last state 3BL) set (or stored) in the DL latches. A programming voltage can then be determined based on the initial programming voltage and the adjusted verification information. For example, the programming voltage can be determined by subtracting a delta voltage from the initial programming voltage according to the adjusted verification information. The programming voltage can thus be applied on the data lines (e.g., BL 516) of the memory cells and further coupled to the gates of the memory cells to program the memory cells for the next state (e.g., LV3).

[0094] FIG. 14 is a simplified block diagram of a memory device 1001 according to an embodiment of the disclosure, and on which various embodiments of the disclosure can be implemented. The memory device 1001 can include a memory array 1004 arranged in rows and columns. The memory array 1004 can include a plurality of channel structures that are formed in a stack of alternating word line layers and insulating layers. A row decode circuit 1008 and a column decode circuit 1010 are provided to decode address signals provided to the memory device 1001. Address signals are received and decoded to access the memory array 1004. Memory device 1001 can also include an input/output (I/O) control circuit 1012 to manage input of commands, addresses and data to the memory device 1001 as well as output of data and status information from the memory device 1001. An address register 1014 is coupled between the I/O control circuit 1012 and the row decode circuit 1008 and column decode circuit 1010 to latch the address signals prior to decoding. A command register 1024 is coupled between the I/O control circuit 1012 and a control logic (or control circuitry) 1016 to latch incoming commands.

[0095] The control logic 1016 can control access to the memory array 1004 in response to the commands and generate status information for the external processor 1030. The control logic 1016 is coupled to the row decode circuit 1008 and the column decode circuit 1010 to control the row decode circuit 1008 and column decode circuit 1010 in response to the addresses. The control logic 1016 can be also coupled to sense amplifier and latch circuitry (also referred to cache circuit) 1018 to control the sense amplifier and latch circuitry 1018 in response to the commands and generate status information for the external processor 1030. In some embodiments, the control logic 1016 can include a verification level counter that is mentioned above. The sense amplifier and latch circuitry 1018 can be coupled to the memory array 1004 and can latch data, either incoming or outgoing, in the form of analog voltage levels. The sense amplifier and latch circuitry 1018 can include page buffers (e.g., the page buffer 500A), verification circuits (e.g., verification circuit 514), and BL bias circuits (e.g., the BL bias circuit 512) described above with respect to FIGS. 5A and 5B.

[0096] Still referring to FIG. 14, a status register 1022 can be coupled between the I/O control circuit 1012 and the control logic 1016 to latch the status information for output to the external processor 1030. The memory device 1001 receives control signals at control logic 1016 over a control link 1032. The control signals may include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, and a write enable WE #. The memory device 1001 may receive commands in the form of command signals, addresses in the form of address signals, and data in the form of data signals from an external processor over a multiplexed input/output (I/O) bus 1034 and output data to the external processor over the I/O bus 1034.

[0097] The various embodiments described herein offer several advantages over related 3D-NAND devices. For example, in the related 3D-NAND devices, page buffers that include six latches are required for programming triple level cells of the related 3D-NAND devices. In the disclosure, a sensing scheme, which can be referred to as a non-inhibit verification, is provided for programming triple level cells of a 3D-NAND device. In the non-inhibit verification, a page buffer that includes five latches can be applied during the programming operation. Accordingly, a latch can be saved in the 3D-NAND as compared to the related 3D-NAND devices. In addition, in the non-inhibit verification, less page buffer operations can be applied when verification levels are switched.

[0098] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.