Bias circuit elements for applying voltages/currents to a photodetector are described. Bias circuit elements described are active devices, e.g. mosfets, directly connected to the photodetector signal point, which inject noise that will be amplified/integrated. Lowering 1/f noise in these bias devices uses multiple parallel mosfets and switching the parallel mosfets gates between a bias activation level signal and a voltage sufficient to drive the mosfet into accumulation Gate switching may be accomplished by at least two partially out of phase clocking signals, with at least one parallel mosfet applying bias while another is in accumulation in continuously switched time periods. Gate switching at a frequency higher than the imaging bandwidth, will have negligible effect on the image signal. During the accumulation phase traps present within the conducting channel of each MOSFET will be depopulated, essentially resetting the MOSFET's 1/f noise, allowing for long integration times while controlling 1/f noise.

Bias circuit elements for applying voltages/currents to a photodetector are described. Bias circuit elements described are active devices, e.g. mosfets, directly connected to the photodetector signal point, which inject noise that will be amplified/integrated. Lowering 1/f noise in these bias devices uses multiple parallel mosfets and switching the parallel mosfets gates between a bias activation level signal and a voltage sufficient to drive the mosfet into accumulation Gate switching may be accomplished by at least two partially out of phase clocking signals, with at least one parallel mosfet applying bias while another is in accumulation in continuously switched time periods. Gate switching at a frequency higher than the imaging bandwidth, will have negligible effect on the image signal. During the accumulation phase traps present within the conducting channel of each MOSFET will be depopulated, essentially resetting the MOSFET's 1/f noise, allowing for long integration times while controlling 1/f noise.

Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.

Techniques for facilitating burn-in mitigation and associated imaging systems and methods are provided. In one example, a method applying a bias signal to a sensor array of an imaging device to increase a temperature of the sensor array to perform burn-in mitigation. The method further includes reducing the temperature of the sensor array. The method further includes determining whether a burn-in is present in the sensor array. Related systems and devices are also provided.

A trigger sense circuit includes a pseudo-differential comparator circuit in signal communication with a pixel array. The pseudo-differential comparator circuit includes a first input in signal communication with a reference pixel group included in the pixel array to receive a pixel reference voltage, and a second input in signal communication with a target pixel group included in the pixel array to receive a pixel target voltage. The pseudo-differential comparator circuit is configured to selectively operate in a calibration mode to remove false trigger events and a comparison mode to detect at least one overheated pixel included in the target pixel group.

A trigger sense circuit includes a pseudo-differential comparator circuit in signal communication with a pixel array. The pseudo-differential comparator circuit includes a first input in signal communication with a reference pixel group included in the pixel array to receive a pixel reference voltage, and a second input in signal communication with a target pixel group included in the pixel array to receive a pixel target voltage. The pseudo-differential comparator circuit is configured to selectively operate in a calibration mode to remove false trigger events and a comparison mode to detect at least one overheated pixel included in the target pixel group.

A resistive element array circuit includes word lines, bit lines, resistive elements, a selector, a differential amplifier, and a ground terminal. The word lines are coupled to a power supply. The resistive elements are each disposed at an intersection of corresponding one of the word lines and corresponding one of the bit lines. The selector is configured to select one word line and one bit line. The differential amplifier includes a positive input terminal configured to be coupled to the selected one of the bit lines which is selected by the selector, a negative input terminal configured to be coupled to non-selected one of the bit lines which is not selected by the selector and to non-selected one of the word lines which is not selected by the selector, an output terminal being coupled to the negative input terminal. The ground terminal is coupled to the positive input terminal.

Techniques for facilitating vacuum health detection for imaging systems and methods are provided. In one example, an imaging device includes a detector configured to generate a first reference signal. The imaging device further includes a buffer circuit configured to store a value of the first reference signal. The imaging device further includes a processing circuit coupled to the buffer circuit. The processing circuit is configured to determine a first predetermined value based on a first temperature associated with the detector. The processing circuit is further configured to determine vacuum integrity associated with the detector based at least on the value of the first reference signal and the first predetermined value. Related methods and systems are also provided.

A device including a sensor is disclosed. In one embodiment, the sensor includes a thermal infrared sensor or a sensor based on CMOS-SOI-MEMS technology (also referred to as “TMOS”). The sensor is capable of performing at least two functions at the same time. The first is remote temperature measurement and the second is presence detection. The sensor passively collects infrared information and a microprocessor coupled to the sensor determines the temperature as well as presence.

A device including a sensor is disclosed. In one embodiment, the sensor includes a thermal infrared sensor or a sensor based on CMOS-SOI-MEMS technology (also referred to as “TMOS”). The sensor is capable of performing at least two functions at the same time. The first is remote temperature measurement and the second is presence detection. The sensor passively collects infrared information and a microprocessor coupled to the sensor determines the temperature as well as presence.