A probe card for testing a device under test having a plurality of contact pads includes a support plate having first contact pads thereon. A flexible membrane has a first face and a peripheral portion including second contact pads thereon. A plurality of contact probes are associated with a first face of the flexible membrane and are configured to abut onto the plurality of contact pads of the device under test. A sliding contact area includes: the first contact pads formed on the support plate; the second contact pads formed on the peripheral portion of the flexible membrane, the peripheral portion of the flexible membrane configured to come in pressing contact onto the support plate at the sliding contact area. A pressing element contacts the peripheral portion of the flexible membrane at the sliding contact area, and the pressing element puts the second contact pads into pressing contact with the first contact pads.

An electrical characterization and fault isolation probe can include a cable, a connector, and a coating over a portion of the cable. The cable can have a first conductor having a first impedance, a second conductor having a second impedance, and a dielectric surrounding the first conductor and electrically isolating the first conductor from the second conductor. The connector can physically couple to, and be in electrical communication with, the cable. The connector can include a first electrical communication pathway and a second electrical communication pathway. The first electrical communication pathway can be electrically isolated from the second electrical communication pathway. The first electrical communication pathway can be in electrical communication with the first conductor. The second electrical communication pathway can be in electrical communication with the second conductor. The connector can have a fifth impedance.

The present disclosure relates to a coaxial lead structure and method for radiating a GIS partial discharge UHF signal outward. The structure includes a GIS cavity, a circular hole provided on the GIS cavity, a medium cylinder provided at the circular hole and sealing the circular hole, a thin cylindrical metal lead that extends into and is fixed to the medium cylinder, and a ground lead connected to the thin cylindrical metal lead. According to the present disclosure, a relatively strong signal may be obtained outside a coaxial lead structure, and detection of a partial discharge UHF signal at this position may increase the detection sensitivity by one time compared with the detection methods of built-in and external disc insulators.

Disclosed is a test device for testing a high-frequency and high-speed semiconductor. The test device includes a probe supporting block formed with a tube accommodating portion along a test direction; a conductive shield tube accommodated in the tube accommodating portion; and a probe accommodated and supported in the shield tube without contact, the tube accommodating portion including a conductive contact portion for transmitting a ground signal to the shield tube. When a high-frequency and high-speed semiconductor or the like subject is tested, the test device easily and inexpensively prevents crosstalk between the adjacent signal probes and improves impedance characteristic.

A multi-section probe and a tapered probe for impedance tuners to broaden the band width of the probes and hence the band width of the tuners. The multi-section probe and the tapered probe are configured to transform the characteristic impedance of the tuner transmission line step-by-step or continuously to a target impedance value.

Embodiments of the disclosure provide a probe structured for electrical and photonics testing of a photonic integrated circuit (PIC) die, the probe including: a membrane having a first surface and an opposing second surface and including conductive traces, the membrane being configured for electrical coupling to a probe interface board (PIB); a set of probe tips positioned on the membrane, the set of probe tips being configured to send electrical test signals to the PIC die or receive electrical test signals from the PIC die; and a photonic test assembly disposed on the membrane and electrically coupled to the conductive traces of the membrane, the photonic test assembly positioned for substantial alignment with a photonic I/O element of the PIC die, wherein the photonic test assembly is configured to transmit a photonic input signal to the photonic I/O element or detect a photonic output signal from the photonic I/O element.

A system and method for reducing inductance and capacitance and shielding signals in an integrated circuit test for devices under test (DUT) is disclosed. Inductance and capacitance are reduced in two ways. First, by recessing the contact pin housing 22 directly into the load board 20 thereby eliminating much of distance between the load board and DUT. Second, surrounding the slot/well 50 in which each RF contact pin resides in the housing with a ground isolation cage 46,46a, 48, 47 of electrically conductive strips or rings at the top and bottom of the housing adjacent the slot with connecting vias thereby creating an isolation cage against RF cross talk transmission and further lowering inductance and capacitance.

A passive slide screw load pull tuner structure can be used on-wafer, in millimeter-wave frequencies from 20 to 110 GHz. It uses a short external (not extended) slabline, mounted sloped and allowing direct contact with the wafer probe, thus permitting the tuning probe to come as close to the wafer probe as physically possible; this minimizes the insertion loss between tuner and DUT and, thus, generates the maximum possible tuning range of a passive electro-mechanical impedance tuner.

Probe systems and methods for testing a device under test are disclosed herein. The probe systems include an electrically conductive ground loop and a structure that is electrically connected to a ground potential via at least a region of the electrically conductive ground loop. The probe systems also include nonlinear circuitry. The nonlinear circuitry is configured to resist flow of electric current within the ground loop when a voltage differential across the nonlinear circuitry is less than a threshold voltage differential and permit flow of electric current within the ground loop when the voltage differential across the nonlinear circuitry is greater than the threshold voltage differential. The methods include positioning a device under test (DUT) within a probe system that includes an electrically conductive ground loop and nonlinear circuitry. The methods also include selectively resisting and permitting electric current flow within the ground loop and through the nonlinear circuitry.

A flexible membrane adapted to carry high-frequency power signals is described having a plurality of contact pads in a central portion of the flexible membrane connected to a plurality of micro contact probes and a plurality of contact structures connected to a support plate in a peripheral portion of the flexible membrane, as well as a plurality of conductive tracks connecting the contact pads with the contact structures. The flexible membrane further includes an intermediate portion between the central and peripheral portions. The elastic membrane is divided into a first area having a first total thickness and into a second area having a second total thickness. The first area is contiguous and adjacent to the second area. The first total thickness is less than or equal to 75 m and the second total thickness is greater than the first total thickness.