A system includes an input voltage source, a linear regulator coupled to the input voltage source, and a load coupled to an output of the linear regulator. The linear regulator includes an error amplifier coupled to a control terminal of a switch; and a control circuit coupled to the error amplifier and configured to provide a reference voltage to the error amplifier. The control circuit includes a mode selection circuit with a slow loop configured to sample a load current and with a fast loop configured to detect an output voltage error signal. The mode selection circuit is configured to adjust a mode of the control circuit between a continuous power mode and a duty cycle power save mode based on the sampled load current and the output voltage error signal.

A noise removing circuit may include: a reference voltage control circuit configured to perform a noise detection sequence operation based on noise detection sequence information, and control a reference voltage based on a counting value; a noise detection circuit configured to compare a supply voltage and the reference voltage, and generate a counting value corresponding to noise which has occurred in the supply voltage; a noise calculation circuit configured to generate a loading control signal corresponding to the noise by performing an operation on the counting value and the reference voltage; and a loading control circuit configured to control a loading value for the supply voltage based on the loading control signal.

An apparatus includes a circuit having an inverter including a power supply, an input terminal and an output terminal, and a harvest terminal electrically coupled to the output terminal. The circuit electrically couples the output terminal and the power supply, such that (1) a harvested charge is transferred from an output voltage at the output terminal to the harvest terminal in response to a high-to-low transition at the circuit and (2) a low-to-high transition at the circuit is driven using at least the harvested charge at the harvest terminal in response to the high-to-low transition.

An aspect of the disclosure relates to an apparatus including: an integrated circuit (IC) including one or more cores, and a current limit detection circuit; a voltage regulator; an inductor coupled between the voltage regulator and the one or more cores of the IC; and a current sensing circuit including inputs coupled across the inductor and an output coupled to the current limit detection circuit of the IC.

An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles.

A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.

A voltage sensing circuit includes voltage regulators, oscillator circuits, delay circuits, and a detector circuit. The detector circuit detects characteristics of signaling received from a first oscillator circuit and characteristics of signaling received from a second oscillator circuit. The detector circuit compares the detected characteristics of the signaling from the first oscillator circuit and the second oscillator circuit to determine whether the detected characteristics from the first oscillator circuit and the second oscillator circuit meet a particular criterion for providing voltage manipulation for the voltage sensing circuit.

A droop reduction circuit on a die includes a voltage detector circuit to detect voltage droop in a supply voltage received by a first load. The droop reduction circuit further includes a driver controller circuit to drive power switch (PSH) banks in response to detection of the voltage droop. Each of the PSH banks includes at least one power switch having an input terminal, a gate terminal, and an output terminal. The input terminal is to receive a secondary voltage, which is higher than the supply voltage and is also received by a second load on the die. The gate terminal is to receive a drive signal from the driver controller, and the output terminal is to pull up the voltage droop in the supply voltage.

A semiconductor package includes an external power supply node, a current monitoring node, and a plurality of semiconductor dies. Each semiconductor die of the plurality of semiconductor dies includes a first circuit and a second circuit. The first circuit is configured to supply a first operating current to that semiconductor die from the external power supply node. The second circuit is configured to measure the first operating current and output the measured first operating current to the current monitoring node. The measured first operating current from each semiconductor die of the plurality of semiconductor dies is summed on the current monitoring node.

The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.