Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

The present disclosure relates to a Flash memory portion architecture coupled to a System-on-Chip (SoC) including a matrix of memory cells with associated decoding and sensing circuitry and having a structurally independent structure linked to the System-on-Chip and comprising: a plurality of sub arrays forming the matrix of memory cells; sense amplifiers coupled to a corresponding sub array; a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers;

A test access port circuit includes a data input terminal, a reset terminal, a mode selection terminal, at least one test data register set, an auxiliary data register set, an instruction register set, and a controller. The controller is coupled to the mode selection terminal and the instruction register set, and controls the at least one test data register set, the auxiliary data register set, and the instruction register set according to at least mode selection signal received by the mode selection terminal. In a reset terminal input mode, when the controller controls a test data register set of the at least one test data register set to store a first input data bit received by the data input terminal, the auxiliary data register set stores a second input data bit received by the reset terminal.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

A distributed control system having at least a distributed control module is disclosed. The distributed control module may be configured to determine a fault state associated with a control loop using a built-in test module. The built-in test module may be incorporated into the distributed control module. The fault state may include no faults, a communication fault, a sensor operation fault, or a controllable component fault. The distributed control module may be configured to transmit a closed-loop control command from the distributed control module to a controllable component when the fault state comprises no faults, or transmit an augmented control command from the distributed control module to the controllable component when the fault state comprises a communication fault or a sensor operation fault, or transmit a disconnect control command from the distributed control module to a controllable component when the fault state comprises a controllable component fault.

A method of assessing a cleanliness of an assembly in a panel during a manufacturing process is provided, wherein an electrical signal of at least one of a predetermined voltage, current or frequency is applied across a first subset and a second subset of nonconnected electrical contacts in a test coupon associated with the assembly, such that the first subset and the second subset have different pitches. In one configuration, the test coupon is tested at higher voltages, currents or frequencies to a point of failure or above a predetermined threshold.

A test method for a semiconductor device includes determining a contact failure between a first semiconductor chip and a second semiconductor chip during assembly of a semiconductor package including the first semiconductor chip and the second semiconductor chip, using a test circuit embedded in the first semiconductor chip, and after the assembly of the semiconductor package, determining whether the semiconductor package is defective by using the test circuit.

A modular computer system includes a plurality of circuit modules, each of which includes one or more components that are subject to failure, such as a vacuum tube. A carrier assembly is added to each circuit module of the modular computer system. The carrier assembly hosts monitoring circuitry that indicates the proper functioning of one or more components on the attached module. In one implementation, each module includes a vacuum tube, and a coil located on the carrier assembly is connected in series with the heater of the vacuum tube. A Hall effect sensor is positioned near the coil. If the heater of the vacuum tube fails, the flow of current through the coil is interrupted and is detected by the Hall effect sensor. The Hall effect sensor is connected to an LED that indicates failure of the vacuum tube.

A method of inspecting a printed circuit board includes confirming whether all parts of the printed circuit board need to be inspected, if inspecting all parts of the printed circuit board, checking pins and vias belonging to each differential signal line on the printed circuit board, and outputting an inspecting result.