Systems and methods are disclosed for IC fabrication by specifying a process monitor with one or more functional blocks including process monitoring structures and wafer identification and die location data on the wafer; fabricating the functional blocks embedded in the wafer at one or more die locations; capturing functional test measurements during or after fabricating the functional blocks; and predicting device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.

A burn in board test device including: a plurality of devices under test, wherein each of the devices under test includes a burn in device; a plurality of resistors connected to each of the plurality of devices under test; a plurality of device under test switches connected to each of the plurality of resistors; and a device under test tester which is connected a plurality of sub input/output (I/O) channels connected to each of the plurality of device under test switches, and a main I/O channel for connecting the plurality of sub I/O channels to each other to test the plurality of devices under test.

A chip testing device and a chip testing system are provided. The chip testing system includes a chip testing device and a plurality of environment control apparatuses. A plurality of electrical connection sockets are disposed on one side of a circuit board, and a plurality of testing modules are disposed on another side of the circuit board. A first fixing member and a second fixing member fix the electrical connection sockets on one side of the circuit board, and no screwing members are required to be screwed between the electrical connection sockets and the circuit board. Each of the electrical connection sockets with a chip disposed thereon can be disposed in a high temperature environment or a low temperature environment for testing along with the chip testing device, so that each of the chips does not need to be detached repeatedly.

The present disclosure relates to a radio frequency (RF) functional probe for testing an RF device in a cryogenic environment. The RF functional probe includes a probe head configured to receive the RF device, a flange structure, an isolation structure coupled between the probe head and the flange structure, and an RF cable structure extending from the flange structure, through the isolation structure, and to the probe head. The isolation structure is configured to provide thermal and electrical isolation to reduce radiant heat leak from the RF cable structure to the RF device. Herein, the isolation structure includes multiple baffle structures, each of which includes cable guides. The cable guides of each baffle structure are configured to guide routing paths for the RF cable structure. The RF cable structure is configured to transmit signals to and from the RF device.

There is provided a design assist apparatus including an inputting unit configured to input an analysis condition including substrate information of a thermal analysis target and current detection element information, and a display control unit configured to control a display unit to display, on the display unit, a thermal analysis result based on the analysis condition, in which the display control unit is configured to control the display unit to display, on the display unit and in a mutually identifiable manner, a first thermal analysis result based on a first analysis condition input by the inputting unit and a second thermal analysis result based on a second analysis condition obtained by changing at least one of the substrate information and the current detection element information from the first analysis condition.

A stress-based aging monitor circuit includes a reference ring oscillator circuit and a stressed ring oscillator circuit that each include transistors like the transistors in a circuit to be monitored. Transistors in the stressed ring oscillator circuit receive a negative gate to source voltage bias while the reference ring oscillator is protected from stress. To measure performance degradation due to stress-based aging, the switching frequencies of the reference ring oscillator circuit and the stressed ring oscillator circuit are compared. The reference ring oscillator and the stressed ring oscillator include stress-enhanced inverter circuits configured to amplify stress-based aging effects to increase sensitivity to the performance degradation caused by stress-based aging. Increased sensitivity increases the precision (e.g., higher resolution) of a supply voltage guard band adjustment used to compensate for the performance degradation to reduce or avoid overcompensating for the effects of stress-based aging.

This document describes techniques and apparatuses including a solder joint damage-prevention mode for a computing device. In general, the computing device may enter the solder joint damage-prevention mode to transfer heat to solder joints and prevent failure mechanisms such as fracture, creep, and/or fatigue. The solder joint damage-prevention mode may rely upon one or more operations, including identifying a state of the computing device in or following which damage to the solder joints has an increased likelihood and, in response, activating a thermal-conditioning system. The thermal-conditioning system may, in general, increase a temperature of the solder joints to improve mechanical robustness of the solder joints.

A method for assessing the state of damage of a semiconductor module that is subject to operational loading, in particular a semiconductor module of a drive system converter, that includes at least one semiconductor component arranged on or in a support structure. It is possible not only to estimate a spent service life for the entire semiconductor module, but also to detect unexpected or undesirable loading states and thus a premature reduction of the remaining service life of the semiconductor module. Continuous load assessments are thus possible already during the operation of the semiconductor module and allow interventions to be made in good time.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs. In one exemplary implementation, the controller directs a portion of sideband testing of a plurality of DUTs concurrently.

The present invention proposes a chip reliability test assembly, which comprises a motherboard and a daughter board. The motherboard is used to support the chips during an aging acceleration process at high temperature. The daughter board is used to measure the electricity of chip after the aging acceleration process. Each chip holder is removable off the motherboard. The daughter board does not go through the aging acceleration process and can be reusable.