Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

A method of testing a device under test (DUT) connected between first and second DUT nodes includes generating a set of control signals, and in response to the set of control signals, disconnecting a first voltage node from a first DUT node, connecting a second voltage node to the first DUT node, periodically connecting and disconnecting a third voltage node to and from the second DUT node at a predetermined frequency, disconnecting a fourth voltage node from the second DUT node when the third voltage node is connected to the second DUT node, and connecting the fourth voltage node to the second DUT node when the third voltage node is disconnected from the second DUT node. A circuit that performs the method is also disclosed.

A method to control aging of a system on chip comprising one or more devices including semiconductor circuit components and at least one aging controller monitoring electrical signals circulating inside the system on chip. The method comprises steps of stressing at least one device of the system on chip by varying hardware parameters related to its operating mode, comparing at least one parameter associated with an electrical signal produced by the at least one device with a reference parameter to determine a difference corresponding to an operating age value of the at least one device, if the operating age value equals or exceeds a threshold age value, determining a stress state value and modifying the operating mode of the at least one device according to the stress state value. A system on chip performing the method is also disclosed.

A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.

A test device includes a diode junction layer having a first dopant conductivity region and a second dopant conductivity region formed within the diode junction layer on opposite sides of a diode junction. A first portion of vertical transistors is formed over the first dopant conductivity region as a device under test, and a second portion of vertical transistors is formed over the second dopant conductivity region. A common source/drain region is formed over the first and second portions of vertical transistors. Current through the first portion of vertical transistors permits measurement of a resistance at a probe contact connected to the common source/drain region.

A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.

An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a current determining circuit configured to determine a cell current and a cell current change rate of at least one of the cells; and a control circuit configured to: determine whether the cell current change rate is outside of a cell current change rate predefined range; and perform a predetermined action if the control circuit determination is positive.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes;