Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

There is a provided a drive circuit in which a first drive signal output circuit includes a first control circuit that controls an output of a first drive signal, and a first abnormality detection circuit that detects an abnormality in a first drive signal output circuit, a second drive signal output circuit includes a second control circuit that controls an output of a second drive signal, and a second abnormality detection circuit that detects an abnormality in a second drive signal output circuit, the first drive signal output circuit transmits an occurrence of abnormality to the second drive signal output circuit, when the first abnormality detection circuit detects the abnormality, and the second drive signal output circuit transmits an occurrence of abnormality to the first drive signal output circuit, when the second abnormality detection circuit detects the abnormality.

A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.

Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.

Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

A computer system includes a circuit board, one or more electronic components and a board management controller (BMC). The electronic components are disposed on the circuit board. The BMC is disposed on the circuit board and electrically connected to the one or more electronic components. The BMC is configured to enable/initiate a boundary scan test for the one or more electronic component.

A semiconductor system includes a first semiconductor device suitable for outputting an external command and a termination control signal and being inputted with a data signal; and a second semiconductor device suitable for generating a termination enable signal in response to the external command and the termination control signal, generating a pull-up signal in response to the termination enable signal, and generating a pull-down signal in response to the termination enable signal and a test mode signal.

A testing system includes a slot configured to receive a device-under-test (DUT), and a core testing processor configured to communicate with a user interface and with the slot, wherein the core testing processor is associated with communication that is independent of any other communications transmitted within the system, and wherein the core testing processor executes a set of tests associated with the DUT.

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.