Technologies are described herein for enabling the automated testing of remote control units by providing a suitable test system that includes a plurality of test stations for simultaneously testing a plurality of remote control units. Each test station includes features that allow it to interact with the remote control unit's inputs, such as buttons and microphone, and outputs, such as IR and RF remote control codes, status LEDs, and audio output. Each test station may be controlled by a controller that executes test scripts or other routines that exercise the functionality of the remote control unit as desired.

A semiconductor package test apparatus is provided. A semiconductor package test apparatus comprises a test board including a plurality of sensors, a chamber into which the test board is loaded, and a controller configured to control a temperature of the chamber, wherein the controller adjusts the temperature using the plurality of sensors.

The present invention relates to a method for testing a device under test. A component of the device under test generates or receives a bus signal, wherein the bus signal comprises a first data signal or a second data signal, and wherein an amplitude of the first data signal is different from an amplitude of the second data signal. A measurement instrument measures an amplitude of the bus signal. Further, it is determined whether the bus signal comprises the first data signal or the second data signal, based on the measured amplitude of the bus signal.

A method and circuit are provided for implementing enhanced scan data testing for test time reduction and decreased scan data interdependence with on product multiple input signature register (OPMISR++) testing, and a design structure on which the subject circuit resides. A respective Pseudo-Random Pattern Generator (PRPG) provides channel input patterns to a respective associated scan channel used for the OPMISR++ diagnostics. Control inputs are coupled to the Pseudo-Random Pattern Generator (PRPG) providing PRPG control distribution. The PRPG selectively provides controlled channel input patterns for the respective scan channel responsive to the control inputs.

A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.

A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

A measurement system includes a measurement module, a processing module, and a display. The measurement module is configured to conduct measurements on a device under test in a repetitive manner in order to obtain measurement results assigned to the repeated measurements. The processing module is configured to combine the measurement results obtained. The processing module is also configured to perform a statistical analysis in a live manner in order to calculate at least one of a live statistical significance parameter of the combined measurement results and a time duration required to obtain a certain statistical significance of the measurement results. The display is configured to display at least one of the live statistical significance parameter and the time duration. Further, a method of providing statistical information is described.

This application discloses a computing system to implement a design verification tool and simulate a circuit design with a regression. The computing system can capture events performed by a circuit design simulated with a regression and identify that one or more combinations of the captured events covers system level functionality of the circuit design. The computing system can determine whether the system level functionality covered by the combinations of the captured events was previously uncovered for the circuit design, and generate a regression efficiency metric configured to quantify newly covered system level functionality prompted by the regression.