A method may involve applying, by a testing computing device, a distortion to a computing device under test. The distortion includes operating the computing device under test at a performance range of a computational resource that could cause the computing device under test to operate outside a normal range. The method may also involve receiving, by the testing computing device and in response to the applying of the distortion, one or more digital signals from the computing device under test. The method may further involve comparing, by the testing computing device, the one or more digital signals to one or more baseline digital signals associated with the computing device under test. The method may also involve detecting, based on the comparing, a presence of at least one anomalous element that could be indicative of a hostile element in the computing device under test.

A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

A logic gate system for fault insertion testing can include a logic gate module having a plurality of input pins. The plurality of input pins can include an input signal pin configured to receive an input signal, a power supply input pin configured to receive power from a power supply, and a test input pin. The logic gate module can also include an output pin connected to the input pins via one or more logic gates. The logic gate system can include a power supply line connected to the power supply input pin and the test input pin. The logic gate system can also include a zero-ohm jumper resistor disposed between the power supply input pin and the test input pin. The zero-ohm resistor can be configured to be replaced with a low ohm resistor to allow reverse driving a voltage on the test input pin. The one or more logic gates can be configured to reverse an output at the output pin when the voltage on the test input pin is reverse driven.

A test and measurement instrument includes one or more ports including at least one test port configured to couple to one or more devices under test, a user interface to receive one or more user inputs, an acquisition memory to store waveform data acquired from the one or more devices under test, one or more processors configured to execute code that causes the one or more processors to: receive an input through the user interface; determine one or more requested data types based on the input; transform the waveform data into compressed data containing only data elements corresponding to the one or more requested data types; and transmit the compressed data to a client. A method of providing usage-aware compressed data from a test and measurement instrument includes acquiring waveform data from one or more devices under test, receiving a user input through a user interface, determining one or more requested data types based on the user input, transforming the waveform data into compressed data containing only data elements corresponding to the one or more requested data types, and transmitting the compressed data to a client.

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.

Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.

The present invention provides a chip test method, apparatus, device, and system. The chip test system may include: a test equipment, including n chip selection signal lines, m sets of first signal lines, and m*n sets of second signal lines; and m*n chip test sites, wherein each chip test site may be coupled to one of the n chip selection signal lines and one of the m sets of first signal lines, each of the m*n chip test sites may correspond to a unique combination of a chip selection signal line and a first signal line coupled thereto, and each chip test site may be correspondingly coupled to one of the m*n sets of second signal lines. According to an embodiment of the present invention, the limited pins of a test equipment may be used to implement individual control of multiple chips.

Controlling of drop test equipment. A predefined test script is obtained over a machine-machine interface. The test script comprises plurality of test settings for drop testing of a device-under-test, DUT. The drop test equipment is controlled to perform drop testing of the DUT according to the test settings of the test script. Test results are collected and provided to a test report.