In an optical device, a first semiconductor layer and a second semiconductor layer are formed to be thinner than a core, an active layer has a shape with an end in a waveguide direction tapers toward a tip end, the first semiconductor layer having a trapezoidal shape with a width thereof decreases toward a side of a third semiconductor layer from a side of the core in a plan view and a width thereof decreases as one end in the waveguide direction recedes from a central portion of the active region, and the second semiconductor layer having a trapezoidal shape with a width thereof decreases toward a side of a fourth semiconductor layer from the side of the core in a plan view and a width thereof decreases as one end in the waveguide direction recedes from the central portion of the active region.

A light receiving device includes, on a substrate, a Si waveguide core provided in a dielectric layer, a first i-type waveguide clad, an i-type core layer, a second i-type waveguide clad, p-type layers disposed on one side of a side surface of a layered structure in a light waveguide direction, the layered structure including the first i-type waveguide clad, the i-type core layer, and the second i-type waveguide clad, n-type layers disposed on the other side, and an electrode on a surface of each of the n-type layers. A width of the Si waveguide core is set to be able to suppress absorption of light in a vicinity of an input edge of the i-type core layer.

A method for fabricating a photonic package device is provided. The method includes patterning a semiconductor layer of a semiconductor-on-insulator (SOI) substrate into a waveguide structure and at least one first semiconductor pillar; forming a metal-dielectric stack over the waveguide structure and the first semiconductor pillar; etching an opening in the metal-dielectric stack to expose the first semiconductor pillar; etching an insulator layer of the SOI substrate to form at least one insulator cap below the first semiconductor pillar; and etching a base semiconductor substrate of the SOI substrate to form at least one second semiconductor pillar below the insulator cap.

A symmetric distributed feedback (DFB) laser that is integrated in a silicon based photonic integrated circuit can output light from both sides of the symmetric DFB laser onto waveguides. The light in the waveguides can be phase adjusted and combined using an optical coupler. The symmetric DFB laser can generate light and symmetrically output light onto different lanes of a multi-lane transmitter.

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

A light detection and ranging system can employ a metal insulator metal tunnel junction positioned atop a substrate. Activation of the metal insulator metal tunnel junction by a signal from a controller can generate light via inelastic scattering. Light to be used to detect downrange targets can be combined from multiple junctions via a multimode interference combiner.

A method of processing by controlling one or more beam characteristics of an optical beam may include: launching the optical beam into a first length of fiber having a first refractive-index profile (RIP); coupling the optical beam from the first length of fiber into a second length of fiber having a second RIP and one or more confinement regions; modifying the one or more beam characteristics of the optical beam in the first length of fiber, in the second length of fiber, or in the first and second lengths of fiber; confining the modified one or more beam characteristics of the optical beam within the one or more confinement regions of the second length of fiber; and/or generating an output beam, having the modified one or more beam characteristics of the optical beam, from the second length of fiber. The first RIP may differ from the second RIP.

A device includes a dielectric layer, a plurality of grating structures, and a dielectric material between the plurality of grating structures and on top of the plurality of grating structures. The grating structures are arranged on the dielectric layer and separated from each other, the plurality of grating structures each having a bottom portion and top portion, the top portion having a first width and the bottom portion having a second width, the second width being larger than the first width.

Optical beam forming at the inputs/outputs of a photonic chip and to the spectral broadening of the light coupled to the chip. The photonic chip comprises an optical waveguide layer supported on a substrate. The chip includes an optical waveguide structure made of silicon and a coupling surface grating. The photonic chip has a front face on the side facing the coupling surface grating and a rear face on the side facing the substrate. A reflecting collimation structure is integrated in the rear face to modify the mode size of an incident light beam. The coupling surface grating is designed to receive light from the optical waveguide structure and to form a light beam directed to the reflecting collimation structure. The invention further relates to the method for producing such a chip.

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.