Patent classifications
G02B2006/12145
In-Plane MEMS Optical Switch
An optical switch includes a first bus waveguide supported by a substrate, an optical antenna suspended over the first bus waveguide via a spring, and interdigitated electrodes coupling the substrate with optical antenna and configured to control a position of the optical antenna relative to the first bus waveguide. When a voltage difference applied to the interdigitated electrodes is less than a lower threshold, the optical antenna is at a first position offset from the first bus waveguide, when the voltage difference applied to the interdigitated electrodes is greater than an upper threshold, the optical antenna is at a second position offset from the first bus waveguide, and the offset at the second position is greater than at the first position.
WAFER-SCALE-INTEGRATED SILICON-PHOTONICS-BASED OPTICAL SWITCHING SYSTEM AND METHOD OF FORMING
A large-scale single-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.
Optical switches based on induced optical loss
An optical device includes a first waveguide that includes a plurality of first portions coupled with regions doped with first dopants, and a plurality of second portions coupled with regions doped with second dopants, distinct from the first dopants, the plurality of first portions being interleaved with the plurality of second portions. And the optical device includes a second waveguide located adjacent to the first waveguide for coupling light from the first waveguide to the second waveguide. The second waveguide includes a third portion coupled with a third region doped with the first dopants and a fourth portion coupled with a fourth region doped with the second dopants, wherein the first portion is located adjacent to the third portion and the second portion is located adjacent to the fourth portion.
OPTICAL SWITCH HAVING LATCHED SWITCH STATES AND ASSOCIATED METHODS
An optical switch has latched switch states and includes optical fibers that are laterally joined together to define an optical switching portion. At least one phase change material (PCM) layer is on the optical switching portion so that a phase of the PCM layer determines a latched switch state from among the latched switch states.
Photonic switches, photonic switching fabrics and methods for data centers
Data center interconnections, which encompass WSCs as well as traditional data centers, have become both a bottleneck and a cost/power issue for cloud computing providers, cloud service providers and the users of the cloud generally. Fiber optic technologies already play critical roles in data center operations and will increasingly in the future. The goal is to move data as fast as possible with the lowest latency with the lowest cost and the smallest space consumption on the server blade and throughout the network. Accordingly, it would be beneficial for new fiber optic interconnection architectures to address the traditional hierarchal time-division multiplexed (TDM) routing and interconnection and provide reduced latency, increased flexibility, lower cost, lower power consumption, and provide interconnections exploiting scalable optical modular optically switched interconnection network as well as temporospatial switching fabrics allowing switching speeds below the slowest switching element within the switching fabric.
Photonic communication platform
Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.
PHOTONIC INTEGRATED CIRCUIT, OPTO-ELECTRONIC SYSTEM AND METHOD
A PIC including a plurality of optically interconnectable functional photonic blocks and a reconfigurable optical connection arrangement having a plurality of semiconductor-based optical waveguides and a plurality of controllable optical switches, at least one controllable optical switch being configurable to be in a first state allowing optical transmission or a second state preventing optical transmission. Depending on the respective first or second state of the at least one controllable optical switch, the optical connection arrangement is configured to enable at least a first set of semiconductor-based optical waveguides to provide at least one optical connection between at least two functional photonic blocks and/or a first optical access path to at least one functional photonic block. An opto-electronic system including the PIC and to a method of improved determination of an overall performance of the PIC.
PHOTONIC COMMUNICATION PLATFORM
Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.
Post-fabrication trimming of silicon ring resonators via integrated annealing
Methods for post-fabrication trimming of a silicon ring resonator are disclosed. Methods include fabricating a heating element, positioned within 2 microns of the silicon ring resonator, subjecting the silicon ring resonator to energetic ion implantation, and annealing the silicon ring resonator, using the heating element. The energetic ion implantation shifts a resonance of the silicon ring resonator towards the red side of the electro-magnetic spectrum. The annealing shifts the resonance of the silicon ring resonator towards the blue side of the electro-magnetic spectrum.
Barium titanate films having reduced interfacial strain
In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.