Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

A layer of amorphous Ge is formed on a substrate using electron-beam evaporation. The evaporation is performed at room temperature. The layer of amorphous Ge has a thickness of at least 50 nm and a purity of at least 90% Ge. The substrate is complementary metal-oxide-semiconductor (CMOS) compatible and is transparent at Long-Wave Infrared (LWIR) wavelengths. The layer of amorphous Ge can be used as a waveguide in chemical sensing and data communication applications. The amorphous Ge waveguide has a transmission loss in the LWIR of 11 dB/cm or less at 8 μm.

A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

A method for fabricating an integrated structure, using a fabrication system having a CMOS line and a photonics line, includes the steps of: in the photonics line, fabricating a first photonics component in a silicon wafer; transferring the wafer from the photonics line to the CMOS line; and in the CMOS line, fabricating a CMOS component in the silicon wafer. Additionally, a monolithic integrated structure includes a silicon wafer with a waveguide and a CMOS component formed therein, wherein the waveguide structure includes a ridge extending away from the upper surface of the silicon wafer. A monolithic integrated structure is also provided which has a photonics component and a CMOS component formed therein, the photonics component including a waveguide having a width of 0.5 μm to 13 μm.

There is set forth herein a photonics device. The photonics device can comprise a substrate, a conductive material formation, a dielectric stack, and a barrier layer. The photonics device can transmit a light signal.

A method for fabricating a thick crack-free dielectric film on a wafer for device fabrication is disclosed herein. A stress-release pattern is fabricated in an oxide layer of the wafer, which surrounds a number of device regions. The stress-release pattern comprises a plurality of recessions, which are spaced periodically along at least one direction. The plurality of recessions interrupt the continuous film during the dielectric film deposition, to prevent cracks from forming in the dielectric film and propagating into the device regions. Such that, a thick crack-free dielectric film can be achieved in the device regions, which are formed by patterning the dielectric layer. Furthermore, conditions of the dielectric film deposition process can be tuned to ensure quality of the deposited dielectric film. Still further, a plurality of deposition runs may be performed to deposit the thick crack-free dielectric film.

A method for fabricating a thick crack-free dielectric film on a wafer for device fabrication is disclosed herein. A stress-release pattern is fabricated in an oxide layer of the wafer, which surrounds a number of device regions. The stress-release pattern comprises a plurality of recessions, which are spaced periodically along at least one direction. The plurality of recessions interrupt the continuous film during the dielectric film deposition, to prevent cracks from forming in the dielectric film and propagating into the device regions. Such that, a thick crack-free dielectric film can be achieved in the device regions, which are formed by patterning the dielectric layer. Furthermore, conditions of the dielectric film deposition process can be tuned to ensure quality of the deposited dielectric film. Still further, a plurality of deposition runs may be performed to deposit the thick crack-free dielectric film.

A semiconductor device comprising a wafer with a preferably single-piece semiconductor substrate, in particular silicon substrate, and at least one integrated electronic component extending in and/or on the semiconductor substrate, the wafer having a front-end-of-line and a back-end-of-line lying there above, the front-end-of-line comprising the integrated electronic component or at least one of the integrated electronic components, and a photonic platform fabricated on the side of the wafer facing away from the front-end-of-line, which photonic platform comprises at least one waveguide and at least one electro-optical device, in particular at least one photodetector and/or at least one electro-optical modulator, wherein the electro-optical device or at least one of the electro-optical devices of the photonic platform is connected to the integrated electronic component or at least one of the integrated electronic components of the wafer.

A semiconductor device comprising a wafer with a preferably single-piece semiconductor substrate, in particular silicon substrate, and at least one integrated electronic component extending in and/or on the semiconductor substrate, the wafer having a front-end-of-line and a back-end-of-line lying there above, the front-end-of-line comprising the integrated electronic component or at least one of the integrated electronic components, and a photonic platform fabricated on the side of the wafer facing away from the front-end-of-line, which photonic platform comprises at least one waveguide and at least one electro-optical device, in particular at least one photodetector and/or at least one electro-optical modulator, wherein the electro-optical device or at least one of the electro-optical devices of the photonic platform is connected to the integrated electronic component or at least one of the integrated electronic components of the wafer.