A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

A low-dropout regulator architecture with undershoot mitigation. In one embodiment, a system including a low-dropout regulator and a digital-to-analog converter (DAC). The low-dropout regulator is configured to generate a load current and output a voltage at an output node. The digital-to-analog converter (DAC) is configured to receive a control input, and output a DAC current to the low-dropout regulator based on the control input. The DAC current is configured to modify the load current and mitigate an undershoot of the voltage that is output at the output node while the voltage transitions from a high voltage level to a low voltage level.

A switched-mode power supply device includes a power switch configured to transfer power from a supply line to a load in switched-mode; a first oscillator configured to operate at a frequency proportional to a voltage of the supply line; a second oscillator configured to operate at a frequency proportional to a voltage of the load; and a regulator configured to operate the power switch according to a duty cycle based on a ratio between the first and second oscillator frequencies.

A switched-mode power supply device includes a power switch configured to transfer power from a supply line to a load in switched-mode; a first oscillator configured to operate at a frequency proportional to a voltage of the supply line; a second oscillator configured to operate at a frequency proportional to a voltage of the load; and a regulator configured to operate the power switch according to a duty cycle based on a ratio between the first and second oscillator frequencies.

A regulating circuit including a first direct current (DC)-DC converter configured to apply a first supply voltage to a first node in a first mode and apply the first supply voltage to a second node in a second mode, a first low drop output (LDO) regulator connected to the first node, the first LDO regulator configured to provide an output voltage to an output node by regulating the first supply voltage of the first node, and a second LDO regulator connected to the first node, the second LDO regulator configured to provide an auxiliary current to the first node in the second mode may be provided.

A pulse width modulated power converter is presented with load-adaptive power transistor scaling scheme using analog-digital hybrid control. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average duty cycle for the given load condition from limit cycle oscillations induced by the coarse adjustments.

Disclosed is a digital LDO regulator capable of performing asynchronous binary search using a binary-weighted PMOS array. The digital LDO regulator includes a PMOS array unit including a binary-weighted PMOS array and that binary searches the PMOS array asynchronously, and a mode determining unit that operates in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the PMOS array unit.

Disclosed is a digital LDO regulator capable of performing asynchronous binary search using a binary-weighted PMOS array. The digital LDO regulator includes a PMOS array unit including a binary-weighted PMOS array and that binary searches the PMOS array asynchronously, and a mode determining unit that operates in at least one of a fine mode, a coarse mode, and a medium mode, based on an output voltage of the PMOS array unit.

In certain aspects, a voltage regulator includes a pass n-type field effect transistor (NFET) coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor (PFET) coupled between the first voltage rail and the second voltage rail. The voltage regulator also includes a first amplifier having an output, a first switch coupled between the output of the first amplifier and a gate of the pass NFET, a second amplifier having an output, and a second switch coupled between the output of the second amplifier and a gate of the pass PFET, a third switch coupled between the gate of the pass NFET and a ground, and a fourth switch coupled between the gate of the pass PFET and the second voltage rail.

Apparatus and methods for a bias supply circuit to support power supply including a switched-mode voltage converter cascaded with an n-channel-based linear regulator are provided. In an example, a cascaded power supply system can include a switched-mode DC-to-DC power converter, including an input voltage node, a first stage output voltage node, and a bootstrapped floating bias voltage node, and a linear regulator circuit. The linear regulator circuit can include an n-channel field-effect transistor (NFET) pass transistor, including a drain terminal coupled to the first stage output voltage node, a gate terminal, and a source terminal configured to provide a second-stage output voltage, and a gate driver circuit, including a driver output coupled to the gate terminal of the NFET pass transistor, and a high side supply node configured to receive a bias voltage generated from the bootstrapped floating bias voltage node.