A circuit may include a first voltage regulator to supply a main circuit and a second voltage regulator to supply a test circuit. The test circuit may produce a test signal having a characteristic dependent on the second regulated supply voltage. A controller may adjust second voltage regulator to a threshold level to induce a change in the characteristic of the test signal. The controller may adjust the first voltage regulator based on the threshold level of the second regulated supply voltage.

According to one embodiment, in a semiconductor integrated circuit, a first input terminal of an error amplifier is electrically connected to a third node between a second node and a reference potential. A second input terminal of the error amplifier is electrically connected to a reference voltage. An output terminal of the error amplifier is electrically connected to a gate of an output transistor. A first input terminal of a comparator is electrically connected to a fourth node between the second node and the reference potential. A second input terminal of the comparator is electrically connected to the reference voltage. One end of a coupling capacitance is electrically connected to an output terminal of the comparator. A gate of an auxiliary transistor is electrically connected to the other end of the coupling capacitance. A drain of the auxiliary transistor is electrically connected to the second node.

A power supply comprises an output stage configured to provide a supply current, in order to obtain a supply voltage. The power supply also comprises a digital regulator configured to receive a reference voltage information and a measured voltage information and to provide a control signal. The power supply further comprises an inner analog control loop, wherein the inner analog control loop is configured to provide an analog feedback signal, which is based on the supply voltage, to the output stage, to make an analog regulation contribution to a regulation of the supply voltage. A method for supplying power to a load is also disclosed.

A simultaneous low quiescent current and high performance low dropout (LDO) voltage regulator is disclosed. In some implementations, the LDO voltage regulator includes a first and a second pass transistors configured to receive an input voltage (Vin). The LDO voltage regulator further includes an error amplifying module having a first output, a second output, a first input, and a second input. The error amplifying module can further include a first output stage configured to drive the gate of the first pass transistor during a high performance (HP) mode, and a second output stage configured to drive the gate of the second pass transistor during the HP mode and during a low power (LP) mode.

A simultaneous low quiescent current and high performance low dropout (LDO) voltage regulator is disclosed. In some implementations, the LDO voltage regulator includes a first and a second pass transistors configured to receive an input voltage (Vin). The LDO voltage regulator further includes an error amplifying module having a first output, a second output, a first input, and a second input. The error amplifying module can further include a first output stage configured to drive the gate of the first pass transistor during a high performance (HP) mode, and a second output stage configured to drive the gate of the second pass transistor during the HP mode and during a low power (LP) mode.

The present document relates to a power converter. The power converter may be configured to convert an input voltage at the input of the power converter into an output voltage at an output of the power converter. The power converter may comprise a pass device, a feedback circuit, and a bypass circuit. The pass device may be coupled between the input of the power converter and the output of the power converter. The feedback circuit may be configured to generate, in a voltage regulation mode, a drive signal for driving a control terminal of the pass device. The bypass circuit may be configured to apply, in a bypass mode, a predetermined voltage to the control terminal of the pass device.

This disclosure relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs and after being processed by these three modules, to pull-up or pull-down the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.

This disclosure relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs and after being processed by these three modules, to pull-up or pull-down the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.

A power management integrated circuit including: a first regulator configured to provide a first output signal to a component; a second regulator configured to provide a second output signal to the component; a third regulator configured to provide a third output signal to the component; a power tracker configured to track first, second and third output signals, aggregate an offset voltage with a selection signal, and generate a reference voltage, wherein the selection signal corresponds to one of the first, second and third output signals; and a sub-regulator configured to generate an input voltage corresponding to the reference voltage and provide the generated input voltage to the first, second and third regulators.

A low dropout (LDO) regulator circuit is provided. The LDO regulator circuit may include a pre-regulator circuit to receive a high voltage input voltage and provide a low voltage supply voltage, and an LDO regulator to receive the low voltage supply voltage and provide a low voltage output voltage. The pre-regulator circuit may include an input stage, an output stage coupled to the input stage, and a first MOSFET coupled to the output stage to provide the low voltage supply voltage. The input stage and first MOSFET may receive the high voltage input voltage. The LDO regulator may include a second MOSFET coupled to the first MOSFET, and may receive the low voltage supply voltage and provide the low voltage output voltage.