A power supply circuit in an embodiment includes a series circuit of a first resistor and a second transistor, the series circuit being connected in parallel to a first transistor between an input terminal and an output terminal, a third transistor configured to output an electric current corresponding to an electric current flowing to the first resistor, a third resistor configured to generate a voltage corresponding to the electric current, and a second operational amplifier configured to output a signal corresponding to a voltage difference between the voltage and a reference voltage to a gate of the first transistor and a gate of the second transistor.

A power supply circuit in an embodiment includes a series circuit of a first resistor and a second transistor, the series circuit being connected in parallel to a first transistor between an input terminal and an output terminal, a third transistor configured to output an electric current corresponding to an electric current flowing to the first resistor, a third resistor configured to generate a voltage corresponding to the electric current, and a second operational amplifier configured to output a signal corresponding to a voltage difference between the voltage and a reference voltage to a gate of the first transistor and a gate of the second transistor.

A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.

A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.

An apparatus and method are provided for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by the effects of aging on the power transistors of the DLDO, such as by the effects of negative bias temperature instability (NBTI)-induced aging, for example. The apparatus comprises a shift register for use in a DLDO that is configured to activate and deactivate power transistors of the DLDO to evenly distribute electrical stress among the transistors in a way that mitigates performance degradation of the DLDO under various load current conditions. In addition, the shift register and methodology can be implemented in such a way that nearly no extra power and area overhead are consumed.

An apparatus and method are provided for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by the effects of aging on the power transistors of the DLDO, such as by the effects of negative bias temperature instability (NBTI)-induced aging, for example. The apparatus comprises a shift register for use in a DLDO that is configured to activate and deactivate power transistors of the DLDO to evenly distribute electrical stress among the transistors in a way that mitigates performance degradation of the DLDO under various load current conditions. In addition, the shift register and methodology can be implemented in such a way that nearly no extra power and area overhead are consumed.

A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.

A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time.

An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.

An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.