A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency f.sub.CLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2.sup.n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f.sub.CLK, to produce a full-speed serialized digital output having 2.sup.n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f.sub.OUT=(M/2.sup.n)×f.sub.CLK.

A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency f.sub.CLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2.sup.n)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f.sub.CLK, to produce a full-speed serialized digital output having 2.sup.n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f.sub.OUT=(M/2.sup.n)×f.sub.CLK.

Apparatus and method for specifying quantum operations such as qubit rotations in a quantum instruction. For example, one embodiment of an apparatus comprises: a quantum instruction processing pipeline to process a quantum instruction having one or more opcodes to specify quantum operations and one or more operands and/or fields to specify values to be used to perform the quantum operations; a quantum waveform synthesizer to synthesize a waveform to control a qubit based on the values specified by the operands and/or fields of the quantum instruction.

A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.

An arbitrary waveform sequencer device for playing a list of at least a first and a second arbitrary waveform file in a sequence is provided. The arbitrary waveform sequencer device comprises a list increment condition control unit configured to control an increment from the first to the second arbitrary waveform file as a function of an increment condition, and a transition control unit configured to control a timing of the increment.

Technology directed to low-emissions touch controller in in-cell touch display systems is described. One in-cell touch controller includes a signal generator circuit that is configured to generate a sense signal according to a sensing function, the sense signal including a windowed sinusoidal waveform. The controller generates a transition signal to transition the in-cell touch display between a display function and the sensing function. The controller drives the sense signal and the transition signal on common voltage (VCOM) layer of electrodes during a touch scanning interval. During a display function interval an integrated display driver is configured to drive a first signal on the VCOM layer of electrodes during a display function interval.

The present invention relates to a function generator made of one apparatus which stabilizes the amplitude of an oscillating triangle signal while canceling offset in the preferred embodiment. A second apparatus is provided which manipulates the stable triangle wave to generate signals of different shapes. The signal shape can be chosen using toggle switches, before setting the amplitude and offset level by an operator. The frequency can be manipulated by editing the original triangle oscillator circuit. A third apparatus measures the amplitudes, offset and pulse width using original software techniques based on specific conditioning circuits, which are coupled to a microcontroller. The microcontroller also measures the frequency of a square wave using hysteresis with two overlapping frequency measurement libraries.

A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (MB), and the n-bit accumulator accumulates by a step size of the digital product (MB), at a rate of a low-speed reference clock of frequency f.sub.CLK/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2.sup.n)2 radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f.sub.CLK, to produce a full-speed serialized digital output having 2.sup.n/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f.sub.OUT=(M/2.sup.n)f.sub.CLK.

A testing device and a method for testing a device under test are provided. The testing device comprises at least two signal generators, at least two numerically controlled oscillators, at least two white gaussian noise generators, at least two digital filters, each of which comprising a respective transfer function H.sub.i at least two adders, at least two digital-to-analog converters, and an analog processor.

A frequency synthesis system includes a memory to store first and second digital control word pairs that each include a first and second control word. A first DAC system generates an analog sampling signal having a first sampling frequency based on a fixed clock signal and the first control word of the first pair during a first time duration having a second sampling frequency based on the first control word of the second pair during a second time duration. A second DAC system generates an analog output signal based on the second control word of the first pair and the first sampling frequency at the first time duration and based on the second control word of the second pair and the second sampling frequency at the second time duration. The analog output signal has a same predetermined output frequency at both the first and second time durations.