A recording control apparatus configured to access a plurality of recording media, includes a control unit configured to set a temperature threshold of each of first and second recording media, a functional restriction being imposed on the recording medium at the temperature threshold, wherein the control unit is configured to, in recording data read from the first recording medium into the second recording medium, make a first setting for the first recording medium and a second setting for the second recording medium, where the first setting includes setting the temperature threshold of the recording medium at which the functional restriction is imposed on the recording medium to a default value of the recording medium, and the second setting includes setting the temperature threshold of the recording medium at which the functional restriction is imposed on the recording medium to a value greater than the default value of the recording medium.

Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

A system includes a parser that receives and parses source code for a reconfigurable dataflow processor, a tensor expression extractor configured to extract tensor indexing expressions from the source code, a logical memory constraint generator that converts the tensor indexing expressions to logical memory indexing constraints, a grouping module that groups the logical memory indexing constraints into concurrent access groups and a memory partitioning module that determines a memory unit partitioning solution for each concurrent access group. The system also includes reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric. The reconfigurable dataflow processor may be configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution. A corresponding method and computer-readable medium are also disclosed herein.

An array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. The array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. The array controller further comprises a control unit configured to enable a communication path between the solid state drive controller and one of the non-volatile storage units according to an address received from the solid state drive controller.

A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Preventing applications from overconsuming shared storage resources, including: identifying one or more sub-regions of data stored on a storage device that are associated with an application of a known application type; compiling information describing the application's utilization of a storage system; determining that a storage system objective has not been met; and initiating, based on the information describing the application's utilization of the storage system, remediation actions.

To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.

A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.

A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules, The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.