An device is disclosed. A first buffer to store a query data point, and a second buffer to store a matrix of candidate data points. A processing element may process the query data point and the matrix of candidate data points to identify candidate data points in the matrix of candidate data points that are nearest to the query data point.

An information processing apparatus performs first migration processing of migrating data from a relatively-old-generation magnetic tape included in one storage pool of a plurality of storage pools to relatively-new-generation magnetic tapes included in each of the plurality of storage pools in a case where a total value of free capacities of the relatively-new-generation magnetic tapes in each of the plurality of storage pools is equal to or larger than a threshold value, and performs second migration processing of migrating data from a plurality of migration-source magnetic tapes included in the storage pool to migration-destination magnetic tapes of which the number is smaller than the number of the migration-source magnetic tapes in a case where the total value is smaller than the threshold value.

Systems and methods including a framework for migration of live data. The method may comprised, by one or more hardware processors executing program instructions, receiving, at a migration proxy of the framework, code for reading data and writing data compatible with each of a plurality of states of a migration of data in a data store, wherein a service is at least intermittently reading data from and writing data to the data store; determining, by a migration runner of the framework, to perform the migration of the data; initiating, by the migration runner, the migration of the data, wherein the migration comprises a plurality of stages; storing, as the migration progresses through the plurality of stages, and at a migration data store of the framework, a current stage of the migration; and during the migration, using the migration proxy to read data from and write data to the data store.

A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

A reconfigurable compute fabric of a system can include multiple nodes, and each node can include multiple, communicatively coupled tiles with respective processing and storage elements. In an example, a tile-based processor can be configured to perform operations comprising receiving a first stencil that defines input data for a first operation. The stencil can have a height corresponding to N rows in a main memory and a stencil width corresponding to M columns in the main memory. The processor can perform operations comprising establishing N buffers in a tile memory, each buffer having M buffer elements, and populating the M buffer elements of the N buffers using respective information, defined by the first stencil, from the main memory. Tile-based stencil operations can use information from the N buffers and provide compute results in an output array.

A storage device according to the present technology may include a memory device for storing data, a buffer memory configured to temporarily store data to be stored in the memory device, and a memory controller configured to determine a delay time based on a plurality of parameters upon receipt of a write request from a host, and transmit a data request to the host after the delay time has elapsed.

Computer-implemented methods for optimized compute resource addition and removal in a distributed storage platform. In a case of a newly added compute resource being connected to a storage subsystem shared by compute resources in the distributed storage platform, the distributed storage platform formulates a redistribution plan to redistribute a subset of a global address space of the storage subsystem to a newly added logical volume in the storage subsystem. In a case of a removed compute resource being disconnected from the storage subsystem, the distributed storage platform formulates a redistribution plan to redistribute respective logical blocks in a logical volume for the removed compute resource to respective remaining logical volumes for respective remaining compute resources in the distributed storage platform. The distributed storage platform executes the redistribution plan to reassign data block ownerships on one or more physical memory devices in the storage subsystem.

A traditional storage platform performs many basic functions, such as storage partitions allocation (i.e., namespace masking) and many advanced functions, such as deduplication or dynamic storage allocation. These functions need to be managed and this results in a multiple management system paradigm, in which a fabric management application manages the fabric connectivity policies (i.e., Zoning), while a storage management application manages the storage namespace mappings and advanced functions. Embodiments herein provide for centralized management for both connectivity and storage namespace mapping, among other advanced features. Namespace zoning information may comprise Namespace ZoneGroups, Namespace Zones, Namespace Zone Members, Namespace ZoneAlias, and Namespace ZoneAlias Members, which expand the NVMe-oF zoning framework from just connectivity control to full Namespaces allocation.

A memory device with non-volatile memory and persistent predictive prefetching provides highspeed storage to a computer system. The memory device uses a non-volatile memory to store data and a volatile memory to cache the data from the non-volatile memory. The computer system sends access requests to obtain data in the non-volatile memory. A prediction engine in the memory device receives the access requests. The prediction engine compute access histories based on the access requests and stores them in an access history table. The prediction engine computes prediction of non-volatile memory addresses that will be accessed in the future based on the stored access history table. The prediction engine causes to store the data from the predicted addresses of the non-volatile memory in the volatile memory. The memory device stores the prediction in the non-volatile memory so the past predictions can be used after restarting the computer system.

A host Flash Translation Layer (FTL) synchronizes host FTL operations with the drive FTL operations to reduce write amplification and over-provisioning. Embodiments of FTL synchronization map, at the host FTL software (SW) stack level, logical bands in which data is managed, referred to as host bands, to the physical bands on a drive where data is stored. The host FTL tracks validity levels of data managed in host bands to determine validity levels of data stored in corresponding physical bands, and optimizes defragmentation operations (such as garbage collection processes and trim operations) applied by the host FTL SW stack to the physical bands based on the tracked validity levels.