Systems and methods are described for resource-efficient memory deduplication and write-protection. In an example, a method includes receiving, by a computing device having a processor, a request to assess deduplication for a plurality of candidate files. The computing device may perform one or more iterative steps for deduplication. The iterative steps may include: receiving, from the plurality of candidate files, a candidate file that is not write-protected; determining, based on a predetermined Bernoulli distribution, a decision to write-protect the candidate file; rendering the candidate file as a write-protected candidate file; determining, based on a review of other candidate files from the plurality of candidate files, that the write-protected candidate file can be deduplicated; and deduplicating the write-protected candidate file.

Methods, systems, and devices for read latency and suspend modes are described. A memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. The memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. For example, the host system may transmit a command including the indication to switch to the second mode of operation. In another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. Based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.

Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

A method of operating a non-volatile memory device is provided. The device includes a latch, a page buffer and blocks, each of which includes pages. The method includes: receiving a page command for a write operation corresponding to a page of one of the blocks; receiving a write command for writing data to the page buffer; latching preexisting latched data or random data generated as latched data; writing the latched data to a page of a new block from among the plurality of blocks that corresponds to a page address based on the write command; and repeatedly updating the page address and repeatedly writing the latched data to additional pages corresponding to each updated page address until each page of the new block has been written to.

A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

Systems and methods to read records of a data staging table, where each record of the data staging table is associated with a package identifier, a key value of a record of a first database table, values of one or more non-key fields of the record of the first database table, and a database operation, include reading of one or more records of the data staging table, each of the read one or more records associated with a package identifier indicating the record is not being processed, and not including a same key value as any other record of the data staging table associated with a package identifier indicating the record is being processed, updating the package identifier of each of the read records of the data staging table to a first package identifier indicating that the record is being processed, creating a transaction record of a transaction queue associating the data staging table and the first package identifier, determining that the read one or more records have been processed, and, in response to the determination, deleting the one or more read rows from the data staging table and the transaction record.

A current operating characteristic value of a unit of the memory device is identified. An operating characteristic threshold value is identified from a set of operating characteristic thresholds, where the current operating characteristic value satisfies an operating characteristic threshold criterion that is based on the operating characteristic threshold value. A set of write-to-read (W2R) delay time thresholds that corresponds to the operating characteristic threshold value is identified from a plurality of sets of W2R delay time thresholds. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, where the W2R threshold criterion is satisfied by a current W2R delay time of the memory sub-system. A read voltage level associated with the identified W2R delay time threshold is identified.

A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

A processing device in a memory system identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field. The processing device identifies a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field. The processing device determines that a value representing a page number stored in the page field satisfies a threshold criterion. Responsive to determining that the value representing the page number satisfies the threshold criterion, the processing device determines a difference between the value representing the page number and a threshold value associated with the threshold criterion plurality of block stripes on a memory device. The processing device stores a value representing the difference as a plurality of bits of the second set of bits. The processing device stores a value representing a block number stored in the block field as a plurality of bits of the first set of bits.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.