A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

Generating a storage interface includes receiving a request for documents, detecting an accounting workflow type corresponding to request, and identifying a document organizational structure matching the accounting workflow type. Further, a virtual storage interface is built using an index on the documents and according to the document organizational structure, and presented.

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

A computing system includes: a storage device, coupled to central processing unit, includes: an in-storage processing engine configured to receive and manage application data from an application executed in a host computer, an in-storage processing coordinator, in the in-storage processing engine, configured to perform in-storage processing with formatted data, based on the application data, includes performing integer math operations, floating point math operations, Boolean operations, reorganization of data bits or symbols, and combinations thereof on the application data, and a data preprocessor, in the in-storage processing coordinator, configured to align the formatted data from the application data to return an in-storage processing output to the application for continued execution.

Disclosed are the SGL processing acceleration method and the storage device. The disclosed SGL processing acceleration method includes: obtaining the SGL associated with the IO command; generating the host space descriptor list and the DTU descriptor list according to the SGL; obtaining one or more host space descriptors of the host space descriptor list according to the DTU descriptor of the DTU descriptor list; and initiating the data transmission according to the obtained one or more host space descriptors.

A data management apparatus, a data management method, and a data storage device are provided. The data management apparatus includes a management unit and a data migration unit. The management unit manages data transmission channels between two types of storage media with different transmission performance. Then, the data migration unit migrates data between the two types of storage media through the managed data transmission channels. In this way, the data management apparatus can directly migrate data between storage media with different transmission performance, and a CPU in a system does not need to perform processing such as instruction conversion and protocol conversion, so that a delay of performing the foregoing processing by the CPU can be shortened. In addition, because the CPU does not need to perform data migration, resource overheads of the CPU can be reduced.

A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.

According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.