A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.

Embodiments of the present disclosure provide a system for accelerated data search of a database storage system. The system includes a host device including a database storage engine; and a memory system including a controller and a memory device, which includes a plurality of pages storing multiple records. The controller includes a page processing accelerator configured to: read, from the plurality of pages, multiple pages in response to a filtered read command; filter particular pages among the multiple pages based on a column full search condition, the filtered pages including entries satisfying the column full search condition; and transfer, to the host device, information regarding the filtered pages.

A method, an electronic device, and a computer program product for inputting and outputting data is disclosed. The method includes receiving a target I/O request for a storage device from an application, determining that a first offset or a second offset is greater than zero, and generating a plurality of I/O requests based on the target address. The I/O requests include a first I/O request for a first data segment in target data and at least one other I/O request for other data segments in the target data. For the first I/O request, the method includes executing a direct I/O operation on the first data segment by bypassing a cache associated with the storage device.

A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.

A description of a snapshot to be generated is received by a local media controller of a memory device, from a memory sub-system controller. The description comprises a memory address range of a memory device. Responsive to detecting a triggering event, a snapshot of the memory address range of the memory device is generated in view of the description. The snapshot is stored to a destination address. The memory sub-system controller is notified of the triggering event.

Aspects of the present disclosure relate to reducing the latency of data deduplication. In embodiments, an input/output (IO) workload received by a storage array is monitored. Further, at least one IO write operation in the IO workload is identified. A space-efficient probabilistic data structure is used to determine if a director board is associated with the IO write. Additionally, the IO write operation is processed based on the determination.

Physical storage devices (PSDs) of a protection group cluster (PGC) may be represented by a protection group matrix (PGM) having a plurality of rows and a plurality of columns, where each row corresponds to a PSD of the PGC, and each column corresponds to a partition of each PSD. The value specified in each cell at an intersection of a row and column specifies the protection group of the PGC to which the partition of the PSD represented by the column and row, respectively, is (or will be) assigned. In response to one or more of PSDs being added to a PGC, the PGM may be reconfigured, including adding new rows, and transposing portions of columns to the new rows, or transposing portions of rows to portions of columns of the new rows. Protection members of the PGC may be re-assigned based on the reconfiguration.

A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may boot an operating system; after booting the operating system, determine that a solid state drive has been hot added to a Peripheral Component Interconnect Express (PCIe) port; suppress discovery of the solid state drive by the operating system; determine a policy associated with the solid state drive; determine that a current configuration associated with the solid state drive does not match a configuration associated with the policy associated with the solid state drive; determine that the configuration associated with the policy can be applied to the solid state drive; apply the configuration associated with the policy to the solid state drive without utilizing the operating system; and inform the operating system that the solid state drive has been communicatively coupled to at least one processor via a PCIe root complex.

Systems, apparatuses and methods may provide for technology that includes a single server to store a portion of a temporal graph to a first memory of the single server, and store a second portion of the temporal graph to a second memory of the single server, wherein an access rate of the first memory is greater than an access rate of the second memory, and wherein a capacity of the second memory is greater than a capacity of the first memory. The single server may also retrieve vertices of the second portion in response to a selectivity of an input query exceeding a cost model threshold.