Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

Systems and methods to read records of a data staging table, where each record of the data staging table is associated with a package identifier, a key value of a record of a first database table, values of one or more non-key fields of the record of the first database table, and a database operation, include reading of one or more records of the data staging table, each of the read one or more records associated with a package identifier indicating the record is not being processed, and not including a same key value as any other record of the data staging table associated with a package identifier indicating the record is being processed, updating the package identifier of each of the read records of the data staging table to a first package identifier indicating that the record is being processed, creating a transaction record of a transaction queue associating the data staging table and the first package identifier, determining that the read one or more records have been processed, and, in response to the determination, deleting the one or more read rows from the data staging table and the transaction record.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.

A method and system for initiating a garbage collection request. Historical data representative of a level of initiated I/O requests is acquired. A first operational state and a second operational state are determined based on the historical data. The first operational state and second operational state are expressed in an indication of the level of initiated I/O requests to be processed. A number of currently initiated I/O requests is acquired. A determination is made as to whether the number of currently initiated I/O requests is indicative of the first operational state or the second operational state. If the computer system is in the first operational state, the garbage collection request is initiated.

One or more aspects of the present disclosure relate to service level input/output scheduling to control central processing unit (CPU) utilization. Input/output (I/O) operations are processed with one or more of a first CPU pool and a second CPU pool of two or more CPU pools. The second CPU pool processes I/O operations that are determined to stall any of the CPU cores.

A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Data from the master die may be provided for a portion of a data burst and data from the slave die may be provided for another portion of the data burst. In some examples, a master die may provide data to one or more slave die. The master die may provide data to the master die and the data to the one or more slave die from a plurality of input terminals. Data from the input terminals may be provided to the slave die for a portion of a data burst and data may be provided from the master die for another portion of the data burst.

An information processing system includes a first storage system for supplying a primary site, and a second storage system for supplying a secondary site. The first storage system is allowed to execute replication by transferring a processing history of a data volume of the first storage system to the second storage system, and to transfer multiple processing histories collectively. The first storage system integrates histories of multiple write accesses included in the multiple processing histories to be collectively transferred, which are duplicatedly addressed on the volume for transfer.

A distributed processing method based on a consistency protocol is provided. The method includes: transmitting a decree prepare request including a first decree number, the decree prepare request requesting other nodes to promise to no longer accept a fast write operation initiated by a leader node whose leader number is less than the first decree number, the first decree number representing a leader number of a current node, and the leader number representing a number of a decree at which the current node that becomes a leader node is located; and in response to receiving decree promises from at least a preset quantity of nodes among the other nodes, enabling the fast write operation from a subsequent decree number of a second decree number determined based on the decree promises, each of the decree promises including the first decree number.