Features are disclosed for forecasting a usage of a block storage volume with a first configuration by a user. A computing device can forecast the usage of the block storage volume based on the historical usage of the block storage volume by the user. The computing device can determine additional potential configurations of the block storage volume. The computing device can further simulate the additional potential configurations of the block storage volume based on the forecasted usage of the block storage volume. The additional potential configurations may include a volume type, a volume size, or other volume characteristics. Based on the simulations of the additional potential configurations, the computing device may determine a recommended configuration. The computing device can dynamically modify the block storage volume based on the recommended configuration of the block storage volume.

Aspects of the present disclosure relate to asynchronous memory management. In embodiments, an input/output (IO) workload is received at a storage array. Further, one or more read-miss events corresponding to the IO workload are identified. Additionally, at least one of the storage array's cache slots is bound to a track identifier (TID) corresponding to the read-miss events based on one or more of the read-miss events' two-dimensional metrics.

A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.

According to one embodiment, a memory system includes a first compression unit, a second compression unit, a non-volatile memory, a first decoding unit, a conversion unit and an output unit. The first compression unit is configured to output second data obtained by compressing first data. The second compression unit is configured to output third data obtained by compressing the second data. Fourth data based on the third data is written to the non-volatile memory. The first decoding unit is configured to decode the third data based on the fourth data to the second data. The conversion unit is configured to acquire fifth data by converting a format of the second data. The output unit is configured to output the fifth data to a host.

In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.

Examples herein describe hardware architecture for processing and accelerating data passing through layers of a neural network. In one embodiment, a reconfigurable integrated circuit (IC) for use with a neural network includes a digital processing engine (DPE) array, each DPE having a plurality of neural network units (NNUs). Each DPE generates different output data based on the currently processing layer of the neural network, with the NNUs parallel processing different input data sets. The reconfigurable IC also includes a plurality of ping-pong buffers designed to alternate storing and processing data for the layers of the neural network.

The present invention provides systems and methods for data storage. A hierarchical storage management architecture is presented to facilitate data management. The disclosed system provides methods for evaluating the state of stored data relative to enterprise needs by using weighted parameters that may be user defined. Also disclosed are systems and methods evaluating costing and risk management associated with stored data.

A method for moving files in a hierarchical storage system having a primary storage and a secondary storage including a sequential storage device from the primary storage to the secondary storage includes obtaining a predetermined file size to be written to the secondary storage, extracting, from a plurality of files in the primary storage, a file not stored in the secondary storage and having the oldest last access time, estimating a file size of the file having the oldest last access time on the secondary storage if the file having the oldest last access time is written to the secondary storage, and selecting the file having the oldest last access time as a file to be moved to the secondary storage as long as the estimated file size does not exceed the predetermined file size to be written to the secondary storage.