Computer implemented systems and methods for migrating datacenter data include providing a quantity of carriers having a data storage capacity, receiving, by the quantity of carriers, a quantity of data stored in a first data storage system having a first location and including erasure coded data blocks. The quantity of carriers migrates to a second data storage system having a second location; and transmits the quantity of data to the second data storage system.

According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.

Embodiments that process data are described. For instance, a method includes receiving, at a first disk management device in a storage system, an access request for accessing data in a plurality of disks associated with the storage system. The method further includes determining whether a first access engine for accessing the plurality of disks in the first disk management device is available. The method further includes redirecting the access request to a second disk management device in the storage system if it is determined that the first access engine is unavailable, wherein a second access engine in the second disk management device is available to access the plurality of disks. By means of this method, effective data access can be performed when an access engine of a disk management device is unavailable, thus realizing a more stable access capability and improving the user experience.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may divide and manage the plurality of memory dies into a plurality of memory die groups, may set a first super memory block including at least one of memory blocks included in a first memory die group, and a second super memory block including at least one of memory blocks included in a second memory die group, may determine whether to set an extended super memory block in which all or part of the first super memory block and all or part of the second super memory block are merged, and may write a write data to the extended super memory block in an interleaving manner when writing the write data requested by a host.

A method for operating a memory system includes: collecting, by a memory controller, information on rows that are determined as row-hammer-attacked in a memory by the memory controller; collecting, by the memory, information on rows that are determined as row-hammer-attacked by the memory; confirming, by the memory, that the row collected by the memory controller is the same as the row collected by the memory; and resetting, by the memory, information on the row collected by the memory which is the same as the row collected by the memory controller in response to the confirmation.

The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.

The present disclosure relates to a storage device. The storage device includes a memory device including write-completed blocks storing data and free blocks each containing no data and a memory controller controlling the memory device to perform a garbage collection operation to store valid data stored in a victim block, among the write-completed blocks, in one of the free blocks based on the number of map segments including mapping information between logical addresses and physical addresses of the valid data, and erase counts of the free blocks.

A data storage system includes multiple head nodes and multiple data storage sleds mounted in a rack. For a particular volume or volume partition one of the head nodes is designated as a primary head node for the volume or volume partition. The primary head node is configured to store data for the volume in a data storage of the primary head node and cause the data to be replicated to a secondary head node. The primary head node is also configured to cause the data for the volume to be stored in a plurality of respective mass storage devices each in different ones of the plurality of data storage sleds of the data storage system.

A synergistic approach to mitigating crosstalk in a Dynamic Random-Access Memory (DRAM) implements the use of a random number generator to increment a counter in a probabilistic manner. The counter is formed by reclaiming bytes of a double data rate (DDR) fault isolation feature. The random number generator value may be compared against a predetermined parameter value and a determination may be made whether or not to extract and increment the counter based on a result of the comparison. A logic controller compares the counter value to a predetermined hotness threshold parameter and a flag is set based on an existence of an address match in local memory. Based on the results of the comparison, access to the DRAM is reduced.

Managed drives of a storage node with different size drives in a fixed arithmetic relationship are organized into clusters of same size drives. Every drive is configured to have M*G same-size partitions, where M is a positive integer variable defined by the arithmetic relationship and G is the RAID group size. The storage capacity of all drives can be viewed as matrices of G+1 rows and M*G columns, and each matrix is composed of submatrices of G+1 rows and G columns. Diagonal spare partitions are allocated and distributed in the same pattern over groups of G columns of all matrices, for increasing partition index values. Members of RAID groups are vertically distributed such that the members of a given RAID group reside in a single partition index of a single cluster. When a drive fails, protection group members of the failed drive are rebuilt in order on spare partitions characterized by lowest partition indices for increasing drive numbers across multiple clusters. Consequently, drive access for rebuild is parallelized and latency is reduced.