A method for determining the memory power consumption includes: receiving a memory control command and controlling an analog memory to enter different working stages according to the memory control command (S410); acquiring an original current change curve of the analog memory in different working stages (S420); determining a target time period corresponding to a target working stage according to a time sequence of the memory control command (S430); intercepting a stage current change curve corresponding to the target working stage from the original current change curve according to the target time period to obtain a target current change curve (S440); selecting target performance parameters from a memory performance parameter table according to the target working stage (S450); and determining the power consumption of the memory according to the target performance parameters and the target current change curve (S460).

Apparatus, systems, and methods are presented for controlling readiness states for partitioned internal resources of a memory controller. The controller may include at least one internal hardware resource that is partitioned so that readiness states for individual partitions of the internal hardware resource are individually controllable. The controller may determine a value for a parameter that corresponds to upcoming workload for the controller. The controller may compare the value to a set of thresholds. The controller may control the readiness states for the partitions of the internal hardware resource based on the comparison of the parameter to the set of thresholds.

A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.

Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

A memory system includes a first nonvolatile memory, a first processor, and a second processor. The first processor sets a first assignment amount. The second processor performs access to the first nonvolatile memory, calculates a consumed amount which is an amount according to an operation time of the first nonvolatile memory in the access, and transmits a notification to the first processor when the consumed amount reaches the first assignment amount.

A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

A data storage device 100 comprising: a non-volatile storage medium 108 configured to store user data 109; a data port 106 configured to transmit data and power between a host computer system 130 and the data storage device 100; a data access state indicator 140; and a controller 110 configured to: selectively set a data access state of the data storage device 100 to either: an unlocked state to enable access to the user data 109; or a locked state to disable access to the user data 109; and generate an indicator control signal to cause the data access state indicator 140 to indicate the data access state, wherein the data access state indicator 140 is configured to indicate the data access state irrespective of whether the data storage device 100 is powered through the data port 106.

In a method of managing a debugging log in a storage device, an event trigger signal is generated based on an external power supply voltage and a plurality of configuration control signals. The event trigger signal is activated in response to an event of interest being issued for generating and storing the debugging log. The debugging log represents information associated with errors occurring in the storage device. The debugging log is generated based on the event trigger signal. The debugging log is stored in a nonvolatile memory. The event of interest includes at least one of a power up event a reset event, a link up event, a link down event or a power down event.

A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system writes, when performing the sudden power-off recovery operation, a plurality of target segments which are segments most recently written to each of the plurality of open memory blocks among the plurality of memory blocks to a target memory block among the plurality of memory blocks.